Tegra: handlers for common and SoC-specific SiP calls
This patch implements a handler for common SiP calls. A weak implementation for the SoC-specific handler has been provided which can be overridden by SoCs to implement any custom SiP calls. Change-Id: I45122892a84ea35d7b44be0f35dc15f6bb95193e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
parent
f6e8ead4a1
commit
d288ab2446
|
@ -59,4 +59,5 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \
|
|||
${COMMON_DIR}/tegra_delay_timer.c \
|
||||
${COMMON_DIR}/tegra_gic.c \
|
||||
${COMMON_DIR}/tegra_pm.c \
|
||||
${COMMON_DIR}/tegra_sip_calls.c \
|
||||
${COMMON_DIR}/tegra_topology.c
|
||||
|
|
|
@ -32,7 +32,6 @@
|
|||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <bl_common.h>
|
||||
#include <context_mgmt.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <memctrl.h>
|
||||
|
@ -40,14 +39,30 @@
|
|||
#include <tegra_private.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra210 SiP SMCs
|
||||
* Common Tegra SiP SMCs
|
||||
******************************************************************************/
|
||||
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
|
||||
|
||||
/*******************************************************************************
|
||||
* SoC specific SiP handler
|
||||
******************************************************************************/
|
||||
#pragma weak plat_sip_handler
|
||||
int plat_sip_handler(uint32_t smc_fid,
|
||||
uint64_t x1,
|
||||
uint64_t x2,
|
||||
uint64_t x3,
|
||||
uint64_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
uint64_t flags)
|
||||
{
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function is responsible for handling all SiP calls from the NS world
|
||||
******************************************************************************/
|
||||
uint64_t tegra210_sip_handler(uint32_t smc_fid,
|
||||
uint64_t tegra_sip_handler(uint32_t smc_fid,
|
||||
uint64_t x1,
|
||||
uint64_t x2,
|
||||
uint64_t x3,
|
||||
|
@ -64,6 +79,11 @@ uint64_t tegra210_sip_handler(uint32_t smc_fid,
|
|||
if (!ns)
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
/* Check if this is a SoC specific SiP */
|
||||
err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
|
||||
if (err == 0)
|
||||
SMC_RET1(handle, err);
|
||||
|
||||
switch (smc_fid) {
|
||||
|
||||
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
|
||||
|
@ -104,11 +124,11 @@ uint64_t tegra210_sip_handler(uint32_t smc_fid,
|
|||
|
||||
/* Define a runtime service descriptor for fast SMC calls */
|
||||
DECLARE_RT_SVC(
|
||||
tegra210_sip_fast,
|
||||
tegra_sip_fast,
|
||||
|
||||
OEN_SIP_START,
|
||||
OEN_SIP_END,
|
||||
SMC_TYPE_FAST,
|
||||
NULL,
|
||||
tegra210_sip_handler
|
||||
tegra_sip_handler
|
||||
);
|
|
@ -35,8 +35,6 @@
|
|||
#include <context_mgmt.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <memctrl.h>
|
||||
#include <runtime_svc.h>
|
||||
#include <tegra_private.h>
|
||||
|
||||
#define NS_SWITCH_AARCH32 1
|
||||
|
@ -45,7 +43,6 @@
|
|||
/*******************************************************************************
|
||||
* Tegra132 SiP SMCs
|
||||
******************************************************************************/
|
||||
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
|
||||
#define TEGRA_SIP_AARCH_SWITCH 0x82000004
|
||||
|
||||
/*******************************************************************************
|
||||
|
@ -56,55 +53,19 @@
|
|||
#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
|
||||
|
||||
/*******************************************************************************
|
||||
* This function is responsible for handling all SiP calls from the NS world
|
||||
* This function is responsible for handling all T132 SiP calls
|
||||
******************************************************************************/
|
||||
uint64_t tegra132_sip_handler(uint32_t smc_fid,
|
||||
uint64_t x1,
|
||||
uint64_t x2,
|
||||
uint64_t x3,
|
||||
uint64_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
uint64_t flags)
|
||||
int plat_sip_handler(uint32_t smc_fid,
|
||||
uint64_t x1,
|
||||
uint64_t x2,
|
||||
uint64_t x3,
|
||||
uint64_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
uint64_t flags)
|
||||
{
|
||||
uint32_t ns;
|
||||
int err;
|
||||
|
||||
/* Determine which security state this SMC originated from */
|
||||
ns = is_caller_non_secure(flags);
|
||||
if (!ns)
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
|
||||
switch (smc_fid) {
|
||||
|
||||
case TEGRA_SIP_NEW_VIDEOMEM_REGION:
|
||||
|
||||
/* clean up the high bits */
|
||||
x1 = (uint32_t)x1;
|
||||
x2 = (uint32_t)x2;
|
||||
|
||||
/*
|
||||
* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
|
||||
* or falls outside of the valid DRAM range
|
||||
*/
|
||||
err = bl31_check_ns_address(x1, x2);
|
||||
if (err)
|
||||
SMC_RET1(handle, err);
|
||||
|
||||
/*
|
||||
* Check if Video Memory is aligned to 1MB.
|
||||
*/
|
||||
if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
|
||||
ERROR("Unaligned Video Memory base address!\n");
|
||||
SMC_RET1(handle, -ENOTSUP);
|
||||
}
|
||||
|
||||
/* new video memory carveout settings */
|
||||
tegra_memctrl_videomem_setup(x1, x2);
|
||||
|
||||
SMC_RET1(handle, 0);
|
||||
break;
|
||||
|
||||
case TEGRA_SIP_AARCH_SWITCH:
|
||||
|
||||
/* clean up the high bits */
|
||||
|
@ -113,7 +74,7 @@ uint64_t tegra132_sip_handler(uint32_t smc_fid,
|
|||
|
||||
if (!x1 || x2 > NS_SWITCH_AARCH32) {
|
||||
ERROR("%s: invalid parameters\n", __func__);
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* x1 = ns entry point */
|
||||
|
@ -125,24 +86,12 @@ uint64_t tegra132_sip_handler(uint32_t smc_fid,
|
|||
|
||||
INFO("CPU switched to AARCH%s mode\n",
|
||||
(x2 == NS_SWITCH_AARCH32) ? "32" : "64");
|
||||
SMC_RET1(handle, 0);
|
||||
break;
|
||||
return 0;
|
||||
|
||||
default:
|
||||
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
|
||||
break;
|
||||
}
|
||||
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
/* Define a runtime service descriptor for fast SMC calls */
|
||||
DECLARE_RT_SVC(
|
||||
tegra132_sip_fast,
|
||||
|
||||
OEN_SIP_START,
|
||||
OEN_SIP_END,
|
||||
SMC_TYPE_FAST,
|
||||
NULL,
|
||||
tegra132_sip_handler
|
||||
);
|
||||
|
|
|
@ -51,7 +51,6 @@ BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
|
|||
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
|
||||
${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \
|
||||
${SOC_DIR}/plat_psci_handlers.c \
|
||||
${SOC_DIR}/plat_sip_calls.c \
|
||||
${SOC_DIR}/plat_setup.c \
|
||||
${SOC_DIR}/plat_secondary.c
|
||||
|
||||
|
|
Loading…
Reference in New Issue