rockchip: Fix GICv2 interrupts
After the removal of deprecated interfaces in TF 2.0 the migration to
the new GIC driver interfaces was done incorrectly in rk3328 and rk3368:
2d6f1f01b1
("rockchip: Migrate to new interfaces").
In the GICv2 driver it is mandated that all interrupts are Group 0
interrupts. This patch simply moves all Group 1 interrupts to Group 0.
Change-Id: I224c0135603eb5b81bd512976361500c0d129a91
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#pragma weak plat_rockchip_gic_pcpu_init
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/******************************************************************************
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* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
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* interrupts.
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* List of interrupts.
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*****************************************************************************/
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static const interrupt_prop_t g0_interrupt_props[] = {
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PLAT_RK_GICV2_G1S_IRQS
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PLAT_RK_GICV2_G0_IRQS
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};
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -131,15 +131,13 @@
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#define RK_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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* Define a list of Group 0 interrupts.
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*/
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#define PLAT_RK_GICV2_G1S_IRQS \
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#define PLAT_RK_GICV2_G0_IRQS \
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INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL), \
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL)
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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#define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/
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#define SHARE_MEM_PAGE_NUM 15
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -96,12 +96,10 @@
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#define RK_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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* Define a list of Group 0 interrupts.
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*/
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#define PLAT_RK_GICV2_G1S_IRQS \
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#define PLAT_RK_GICV2_G0_IRQS \
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INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL)
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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#endif /* RK3368_DEF_H */
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