From d323af9e3d903d981b42f954844a95a6bfef91ab Mon Sep 17 00:00:00 2001 From: Daniel Boulby Date: Fri, 6 Jul 2018 16:54:44 +0100 Subject: [PATCH] Rework page table setup for varying number of mem regions Change arm_setup_page_tables() to take a variable number of memory regions. Remove coherent memory region from BL1, BL2 and BL2U as their coherent memory region doesn't contain anything and therefore has a size of 0. Add check to ensure this doesn't change without us knowing. Change-Id: I790054e3b20b056dda1043a4a67bd7ac2d6a3bc0 Signed-off-by: Daniel Boulby --- include/plat/arm/common/arm_def.h | 19 +++++++ include/plat/arm/common/plat_arm.h | 13 +---- include/plat/arm/css/common/css_def.h | 8 +++ plat/arm/board/common/board_css_common.c | 2 + plat/arm/board/juno/include/platform_def.h | 2 +- plat/arm/common/arm_bl1_setup.c | 34 ++++++++---- plat/arm/common/arm_bl2_el3_setup.c | 28 ++++++---- plat/arm/common/arm_bl2_setup.c | 26 +++++---- plat/arm/common/arm_bl2u_setup.c | 29 ++++++---- plat/arm/common/arm_bl31_setup.c | 24 +++++---- plat/arm/common/arm_common.c | 63 +++++++--------------- plat/arm/common/sp_min/arm_sp_min_setup.c | 24 +++++---- plat/arm/common/tsp/arm_tsp_setup.c | 25 +++++---- plat/ti/k3/common/k3_bl31_setup.c | 18 ++++--- plat/xilinx/zynqmp/bl31_zynqmp_setup.c | 23 +++++--- plat/xilinx/zynqmp/tsp/tsp_plat_setup.c | 23 ++++---- 16 files changed, 216 insertions(+), 145 deletions(-) diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index e3d0edbce..12137ae4c 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -241,6 +241,25 @@ ARM_EL3_TZC_DRAM1_SIZE, \ MT_MEMORY | MT_RW | MT_SECURE) +#if SEPARATE_CODE_AND_RODATA +#define ARM_MAP_BL_CODE MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) +#define ARM_MAP_BL_RO_DATA MAP_REGION_FLAT( \ + BL_RO_DATA_BASE, \ + BL_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) +#endif +#if USE_COHERENT_MEM +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + /* * The number of regions like RO(code), coherent and data required by * different BL stages which need to be mapped in the MMU. diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 33f2c7dbe..c26052afc 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -69,17 +69,8 @@ typedef struct arm_tzc_regions_info { /* * Utility functions common to ARM standard platforms */ -void arm_setup_page_tables(uintptr_t total_base, - size_t total_size, - uintptr_t code_start, - uintptr_t code_limit, - uintptr_t rodata_start, - uintptr_t rodata_limit -#if USE_COHERENT_MEM - , uintptr_t coh_start, - uintptr_t coh_limit -#endif -); +void arm_setup_page_tables(const mmap_region_t bl_regions[], + const mmap_region_t plat_regions[]); #if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) /* diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h index 725c27cbc..048c58a31 100644 --- a/include/plat/arm/css/common/css_def.h +++ b/include/plat/arm/css/common/css_def.h @@ -101,6 +101,14 @@ NSRAM_SIZE, \ MT_DEVICE | MT_RW | MT_NS) +#if defined(IMAGE_BL2U) +#define CSS_MAP_SCP_BL2U MAP_REGION_FLAT( \ + SCP_BL2U_BASE, \ + SCP_BL2U_LIMIT \ + - SCP_BL2U_BASE,\ + MT_RW_DATA | MT_SECURE) +#endif + /* Platform ID address */ #define SSC_VERSION_OFFSET 0x040 diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/common/board_css_common.c index c4e83a427..40b1a275a 100644 --- a/plat/arm/board/common/board_css_common.c +++ b/plat/arm/board/common/board_css_common.c @@ -53,6 +53,8 @@ const mmap_region_t plat_arm_mmap[] = { const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, CSS_MAP_DEVICE, + CSS_MAP_SCP_BL2U, + V2M_MAP_IOFPGA, SOC_CSS_MAP_DEVICE, {0} }; diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index 80d4ba81a..a781c4f09 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -98,7 +98,7 @@ #endif #ifdef IMAGE_BL2U -# define PLAT_ARM_MMAP_ENTRIES 4 +# define PLAT_ARM_MMAP_ENTRIES 5 # define MAX_XLAT_TABLES 3 #endif diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index d141f647e..180eae98b 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -23,6 +24,19 @@ #pragma weak bl1_plat_sec_mem_layout #pragma weak bl1_plat_prepare_exit +#define MAP_BL1_TOTAL MAP_REGION_FLAT( \ + bl1_tzram_layout.total_base, \ + bl1_tzram_layout.total_size, \ + MT_MEMORY | MT_RW | MT_SECURE) +#define MAP_BL1_CODE MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL1_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) +#define MAP_BL1_RO_DATA MAP_REGION_FLAT( \ + BL1_RO_DATA_BASE, \ + BL1_RO_DATA_END \ + - BL_RO_DATA_BASE, \ + MT_RO_DATA | MT_SECURE) /* Data structure which holds the extents of the trusted SRAM for BL1*/ static meminfo_t bl1_tzram_layout; @@ -84,17 +98,19 @@ void bl1_early_platform_setup(void) *****************************************************************************/ void arm_bl1_plat_arch_setup(void) { - arm_setup_page_tables(bl1_tzram_layout.total_base, - bl1_tzram_layout.total_size, - BL_CODE_BASE, - BL1_CODE_END, - BL1_RO_DATA_BASE, - BL1_RO_DATA_END #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + /* ARM platforms dont use coherent memory in BL1 */ + assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif - ); + + const mmap_region_t bl_regions[] = { + MAP_BL1_TOTAL, + MAP_BL1_CODE, + MAP_BL1_RO_DATA, + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); #ifdef AARCH32 enable_mmu_secure(0); #else diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c index e7247c63d..1d602bb1e 100644 --- a/plat/arm/common/arm_bl2_el3_setup.c +++ b/plat/arm/common/arm_bl2_el3_setup.c @@ -3,6 +3,8 @@ * * SPDX-License-Identifier: BSD-3-Clause */ +#include +#include #include #include #include @@ -11,6 +13,11 @@ #pragma weak bl2_el3_plat_arch_setup #pragma weak bl2_el3_plat_prepare_exit +#define MAP_BL2_EL3_TOTAL MAP_REGION_FLAT( \ + bl2_el3_tzram_layout.total_base, \ + bl2_el3_tzram_layout.total_size, \ + MT_MEMORY | MT_RW | MT_SECURE) + static meminfo_t bl2_el3_tzram_layout; /* @@ -60,17 +67,20 @@ void bl2_el3_early_platform_setup(u_register_t arg0 __unused, ******************************************************************************/ void arm_bl2_el3_plat_arch_setup(void) { - arm_setup_page_tables(bl2_el3_tzram_layout.total_base, - bl2_el3_tzram_layout.total_size, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END + #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + /* Ensure ARM platforms dont use coherent memory in BL2_AT_EL3 */ + assert(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE == 0U); #endif - ); + + const mmap_region_t bl_regions[] = { + MAP_BL2_EL3_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); #ifdef AARCH32 enable_mmu_secure(0); diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 3aa99f805..88bf1e6cd 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -35,6 +35,11 @@ CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); #pragma weak bl2_plat_arch_setup #pragma weak bl2_plat_sec_mem_layout +#define MAP_BL2_TOTAL MAP_REGION_FLAT( \ + bl2_tzram_layout.total_base, \ + bl2_tzram_layout.total_size, \ + MT_MEMORY | MT_RW | MT_SECURE) + #if LOAD_IMAGE_V2 #pragma weak bl2_plat_handle_post_image_load @@ -231,17 +236,20 @@ void bl2_platform_setup(void) ******************************************************************************/ void arm_bl2_plat_arch_setup(void) { - arm_setup_page_tables(bl2_tzram_layout.total_base, - bl2_tzram_layout.total_size, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END + #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + /* Ensure ARM platforms dont use coherent memory in BL2 */ + assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif - ); + + const mmap_region_t bl_regions[] = { + MAP_BL2_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); #ifdef AARCH32 enable_mmu_secure(0); diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c index cd691e5c3..77d1186c7 100644 --- a/plat/arm/common/arm_bl2u_setup.c +++ b/plat/arm/common/arm_bl2u_setup.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -18,6 +19,11 @@ #pragma weak bl2u_early_platform_setup #pragma weak bl2u_plat_arch_setup +#define MAP_BL2U_TOTAL MAP_REGION_FLAT( \ + BL2U_BASE, \ + BL2U_LIMIT - BL2U_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + /* * Perform ARM standard platform setup for BL2U */ @@ -58,18 +64,21 @@ void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info) ******************************************************************************/ void arm_bl2u_plat_arch_setup(void) { - arm_setup_page_tables(BL2U_BASE, - BL31_LIMIT, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END + #if USE_COHERENT_MEM - , - BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + /* Ensure ARM platforms dont use coherent memory in BL2U */ + assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif - ); + + const mmap_region_t bl_regions[] = { + MAP_BL2U_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); + #ifdef AARCH32 enable_mmu_secure(0); #else diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 6346f0fff..6be293347 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -37,6 +37,10 @@ CASSERT(BL31_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl31_base_overflows); #pragma weak bl31_plat_arch_setup #pragma weak bl31_plat_get_next_image_ep_info +#define MAP_BL31_TOTAL MAP_REGION_FLAT( \ + BL31_BASE, \ + BL31_END - BL31_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image for the @@ -280,17 +284,19 @@ void bl31_plat_runtime_setup(void) ******************************************************************************/ void arm_bl31_plat_arch_setup(void) { - arm_setup_page_tables(BL31_BASE, - BL31_END - BL31_BASE, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END + + const mmap_region_t bl_regions[] = { + MAP_BL31_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + ARM_MAP_BL_COHERENT_RAM, #endif - ); + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); + enable_mmu_el3(0); } diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 32fd9ee68..52d226846 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -28,61 +28,34 @@ extern const mmap_region_t plat_arm_mmap[]; /* * Set up the page tables for the generic and platform-specific memory regions. - * The extents of the generic memory regions are specified by the function - * arguments and consist of: - * - Trusted SRAM seen by the BL image; + * The size of the Trusted SRAM seen by the BL image must be specified as well + * as an array specifying the generic memory regions which can be; * - Code section; * - Read-only data section; * - Coherent memory region, if applicable. */ -void arm_setup_page_tables(uintptr_t total_base, - size_t total_size, - uintptr_t code_start, - uintptr_t code_limit, - uintptr_t rodata_start, - uintptr_t rodata_limit -#if USE_COHERENT_MEM - , - uintptr_t coh_start, - uintptr_t coh_limit -#endif - ) + +void arm_setup_page_tables(const mmap_region_t bl_regions[], + const mmap_region_t plat_regions[]) { +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + const mmap_region_t *regions = bl_regions; + + while (regions->size != 0U) { + VERBOSE("Region: 0x%lx - 0x%lx has attributes 0x%x\n", + regions->base_va, + (regions->base_va + regions->size), + regions->attr); + regions++; + } +#endif /* * Map the Trusted SRAM with appropriate memory attributes. * Subsequent mappings will adjust the attributes for specific regions. */ - VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", - (void *) total_base, (void *) (total_base + total_size)); - mmap_add_region(total_base, total_base, - total_size, - MT_MEMORY | MT_RW | MT_SECURE); - - /* Re-map the code section */ - VERBOSE("Code region: %p - %p\n", - (void *) code_start, (void *) code_limit); - mmap_add_region(code_start, code_start, - code_limit - code_start, - MT_CODE | MT_SECURE); - - /* Re-map the read-only data section */ - VERBOSE("Read-only data region: %p - %p\n", - (void *) rodata_start, (void *) rodata_limit); - mmap_add_region(rodata_start, rodata_start, - rodata_limit - rodata_start, - MT_RO_DATA | MT_SECURE); - -#if USE_COHERENT_MEM - /* Re-map the coherent memory region */ - VERBOSE("Coherent region: %p - %p\n", - (void *) coh_start, (void *) coh_limit); - mmap_add_region(coh_start, coh_start, - coh_limit - coh_start, - MT_DEVICE | MT_RW | MT_SECURE); -#endif - + mmap_add(bl_regions); /* Now (re-)map the platform-specific memory regions */ - mmap_add(plat_arm_get_mmap()); + mmap_add(plat_regions); /* Create the page tables to reflect the above mappings */ init_xlat_tables(); diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c index b42e35f3a..c7f317c59 100644 --- a/plat/arm/common/sp_min/arm_sp_min_setup.c +++ b/plat/arm/common/sp_min/arm_sp_min_setup.c @@ -22,6 +22,11 @@ static entry_point_info_t bl33_image_ep_info; #pragma weak sp_min_plat_arch_setup #pragma weak plat_arm_sp_min_early_platform_setup +#define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \ + BL32_BASE, \ + BL32_END - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + /* * Check that BL32_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. @@ -196,18 +201,17 @@ void sp_min_plat_runtime_setup(void) ******************************************************************************/ void sp_min_plat_arch_setup(void) { - - arm_setup_page_tables(BL32_BASE, - (BL32_END - BL32_BASE), - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END + const mmap_region_t bl_regions[] = { + MAP_BL_SP_MIN_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + ARM_MAP_BL_COHERENT_RAM, #endif - ); + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_secure(0); } diff --git a/plat/arm/common/tsp/arm_tsp_setup.c b/plat/arm/common/tsp/arm_tsp_setup.c index 16125ad4f..491705dfa 100644 --- a/plat/arm/common/tsp/arm_tsp_setup.c +++ b/plat/arm/common/tsp/arm_tsp_setup.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -20,6 +21,10 @@ #pragma weak tsp_platform_setup #pragma weak tsp_plat_arch_setup +#define MAP_BL_TSP_TOTAL MAP_REGION_FLAT( \ + BL32_BASE, \ + BL32_END - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) /******************************************************************************* * Initialize the UART @@ -69,16 +74,18 @@ void tsp_platform_setup(void) ******************************************************************************/ void tsp_plat_arch_setup(void) { - arm_setup_page_tables(BL32_BASE, - (BL32_END - BL32_BASE), - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END #if USE_COHERENT_MEM - , BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END + /* Ensure ARM platforms dont use coherent memory in TSP */ + assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); #endif - ); + + const mmap_region_t bl_regions[] = { + MAP_BL_TSP_TOTAL, + ARM_MAP_BL_CODE, + ARM_MAP_BL_RO_DATA, + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el1(0); } diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c index ca7d214a1..3de57a7c4 100644 --- a/plat/ti/k3/common/k3_bl31_setup.c +++ b/plat/ti/k3/common/k3_bl31_setup.c @@ -99,12 +99,18 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, void bl31_plat_arch_setup(void) { - arm_setup_page_tables(BL31_BASE, - BL31_END - BL31_BASE, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END); + + const mmap_region_t bl_regions[] = { + MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE), + MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_END, + MT_RO_DATA | MT_SECURE), + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el3(0); } diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 0b3106f7a..abfb8c6fc 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -179,13 +179,20 @@ void bl31_plat_arch_setup(void) plat_arm_interconnect_init(); plat_arm_interconnect_enter_coherency(); - arm_setup_page_tables(BL31_BASE, - BL31_END - BL31_BASE, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END, - BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END); + + const mmap_region_t bl_regions[] = { + MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE), + MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, + MT_RO_DATA | MT_SECURE), + MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, + MT_DEVICE | MT_RW | MT_SECURE), + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el3(0); } diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c index ecc4d0a97..52d4bf8cc 100644 --- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c +++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c @@ -44,14 +44,19 @@ void tsp_platform_setup(void) ******************************************************************************/ void tsp_plat_arch_setup(void) { - arm_setup_page_tables(BL32_BASE, - BL32_END - BL32_BASE, - BL_CODE_BASE, - BL_CODE_END, - BL_RO_DATA_BASE, - BL_RO_DATA_END, - BL_COHERENT_RAM_BASE, - BL_COHERENT_RAM_END - ); + const mmap_region_t bl_regions[] = { + MAP_REGION_FLAT(BL32_BASE, BL32_END - BL32_BASE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, + MT_CODE | MT_SECURE), + MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, + MT_RO_DATA | MT_SECURE), + MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, + BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, + MT_DEVICE | MT_RW | MT_SECURE), + {0} + }; + + arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); enable_mmu_el1(0); }