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feat(plat/mediatek/mt8195): support MCUSYS off when system suspend 

Add drivers to support MCUSYS off when system suspend.

Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I388fd2318f471083158992464ecdf2181fc7d87a
This commit is contained in:
Edward-JW Yang 2021-06-28 11:08:10 +08:00 committed by Rex-BC Chen
parent 048189637e
commit d336e093dd
9 changed files with 138 additions and 10 deletions
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2
plat/mediatek/mt8195/aarch64/platform_common.c
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@ -15,6 +15,8 @@ const mmap_region_t plat_mmap[] = {
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(eDP_SEC_BASE, eDP_SEC_SIZE,

31
plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,6 +12,8 @@
#include <lib/spinlock.h>
#include <mt_cpu_pm_cpc.h>
#include <mt_lp_irqremain.h>
#include <mt_lp_rm.h>
#include <mt_mcdi.h>
#include <plat_mtk_lpm.h>
#include <plat_pm.h>
@ -73,25 +75,48 @@ static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state)
static int pwr_mcusys_pwron_finished(unsigned int cpu,
const psci_power_state_t *state)
{
int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
return -1;
}
mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id);
mt_lp_irqremain_release();
return 0;
}
static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
{
int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
if (!IS_MCUSYS_OFF_STATE(state)) {
goto mt_pwr_mcusysoff_break;
}
if (mcdi_try_init() != 0) { /* not ready to process mcusys-off */
if (mcdi_try_init() != 0) {
goto mt_pwr_mcusysoff_break;
}
if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) {
goto mt_pwr_mcusysoff_break;
}
plat_mt_lp_cpu_rc =
mt_lp_rm_find_and_run_constraint(0, cpu, state_id, NULL);
if (plat_mt_lp_cpu_rc < 0) {
goto mt_pwr_mcusysoff_reflect;
}
mt_lp_irqremain_aquire();
return 0;
mt_pwr_mcusysoff_reflect:
mtk_cpc_mcusys_off_reflect();
mt_pwr_mcusysoff_break:
plat_mt_lp_cpu_rc = -1;
@ -119,5 +144,7 @@ const struct mt_lpm_tz *mt_plat_cpu_pm_init(void)
INFO("MCDI init done.\n");
}
mt_lp_irqremain_init();
return &plat_pm;
}

70
plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c Normal file
View File

@ -0,0 +1,70 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <mt_lp_rm.h>
#include <mt_lp_irqremain.h>
#include <mtk_cirq.h>
#include <plat_mtk_lpm.h>
#define KEYPAD_IRQ_ID U(138)
#define KEYPAD_WAKESRC 0x4
static struct mt_irqremain remain_irqs;
int mt_lp_irqremain_submit(void)
{
if (remain_irqs.count == 0) {
return -1;
}
set_wakeup_sources(remain_irqs.irqs, remain_irqs.count);
mt_lp_rm_do_update(-1, PLAT_RC_UPDATE_REMAIN_IRQS, &remain_irqs);
return 0;
}
int mt_lp_irqremain_aquire(void)
{
if (remain_irqs.count == 0) {
return -1;
}
mt_cirq_sw_reset();
mt_cirq_clone_gic();
mt_cirq_enable();
return 0;
}
int mt_lp_irqremain_release(void)
{
if (remain_irqs.count == 0) {
return -1;
}
mt_cirq_flush();
mt_cirq_disable();
return 0;
}
void mt_lp_irqremain_init(void)
{
uint32_t idx;
remain_irqs.count = 0;
/*edge keypad*/
idx = remain_irqs.count;
remain_irqs.irqs[idx] = KEYPAD_IRQ_ID;
remain_irqs.wakeupsrc_cat[idx] = 0;
remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC;
remain_irqs.count++;
mt_lp_irqremain_submit();
}

14
plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.h Normal file
View File

@ -0,0 +1,14 @@
/*
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_LP_IRQREMAIN_H
#define MT_LP_IRQREMAIN_H
extern int mt_lp_irqremain_submit(void);
extern int mt_lp_irqremain_aquire(void);
extern int mt_lp_irqremain_release(void);
extern void mt_lp_irqremain_init(void);
#endif /* MT_LP_IRQREMAIN_H */

5
plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c
View File

@ -1,10 +1,11 @@
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <cdefs.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
@ -144,5 +145,7 @@ int mcdi_try_init(void)
mcdi_init_status = MCDI_INIT_DONE;
}
INFO("mcdi ready for mcusys-off-idle and system suspend\n");
return (mcdi_init_status == MCDI_INIT_DONE) ? 0 : mcdi_init_status;
}

4
plat/mediatek/mt8195/include/plat_mtk_lpm.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,7 +10,7 @@
#include <lib/psci/psci.h>
#include <lib/utils_def.h>
#define MT_IRQ_REMAIN_MAX U(8)
#define MT_IRQ_REMAIN_MAX U(32)
#define MT_IRQ_REMAIN_CAT_LOG BIT(31)
struct mt_irqremain {

9
plat/mediatek/mt8195/include/platform_def.h
View File

@ -21,7 +21,16 @@
#define MTK_MCDI_SRAM_BASE 0x11B000
#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
#define SPM_BASE (IO_PHYS + 0x00006000)
#define APMIXEDSYS (IO_PHYS + 0x0000C000)
#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
#define VDOSYS0_BASE (IO_PHYS + 0x0C01A000)
#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
/*******************************************************************************
* DP/eDP related constants

8
plat/mediatek/mt8195/plat_pm.c
View File

@ -88,11 +88,6 @@ static void plat_cpu_pwron_common(unsigned int cpu,
/* PTP3 config */
ptp3_core_init(cpu);
/* Enable the GIC CPU interface */
gicv3_rdistif_on(cpu);
gicv3_cpuif_enable(cpu);
mt_gic_rdistif_init();
/*
* If mcusys does power down before then restore
* all CPUs' GIC Redistributors
@ -100,6 +95,9 @@ static void plat_cpu_pwron_common(unsigned int cpu,
if (IS_MCUSYS_OFF_STATE(state)) {
mt_gic_rdistif_restore_all();
} else {
gicv3_rdistif_on(cpu);
gicv3_cpuif_enable(cpu);
mt_gic_rdistif_init();
mt_gic_rdistif_restore();
}
}

5
plat/mediatek/mt8195/platform.mk
View File

@ -12,6 +12,8 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT}/common/drivers/gpio/ \
-I${MTK_PLAT}/common/drivers/rtc/ \
-I${MTK_PLAT}/common/drivers/timer/ \
-I${MTK_PLAT}/common/drivers/uart/ \
-I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT_SOC}/drivers/dp/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
@ -45,6 +47,8 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c \
${MTK_PLAT}/common/drivers/timer/mt_timer.c \
${MTK_PLAT}/common/drivers/uart/uart.c \
${MTK_PLAT}/common/lpm/mt_lp_rm.c \
${MTK_PLAT}/common/mtk_cirq.c \
${MTK_PLAT}/common/mtk_plat_common.c \
${MTK_PLAT}/common/mtk_sip_svc.c \
@ -57,6 +61,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \