From 9b624a7deba7c23ba92589979f2b390f7d73dfd7 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 28 Aug 2020 14:00:15 -0700 Subject: [PATCH 1/7] cpus: denver: introduce macro to declare cpu_ops This patch introduces a macro to declare cpu_op for all Denver SKUs. Signed-off-by: Varun Wadekar Change-Id: Ibcf88c3256fc5dcaa1be855749ebd2c5c396c977 --- lib/cpus/aarch64/denver.S | 79 +++++++++------------------------------ 1 file changed, 18 insertions(+), 61 deletions(-) diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index d662e7f89..834546bf6 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -353,65 +353,22 @@ func denver_cpu_reg_dump ret endfunc denver_cpu_reg_dump -declare_cpu_ops_wa denver, DENVER_MIDR_PN0, \ - denver_reset_func, \ - check_errata_cve_2017_5715, \ - CPU_NO_EXTRA2_FUNC, \ - denver_core_pwr_dwn, \ - denver_cluster_pwr_dwn +/* macro to declare cpu_ops for Denver SKUs */ +.macro denver_cpu_ops_wa midr + declare_cpu_ops_wa denver, \midr, \ + denver_reset_func, \ + check_errata_cve_2017_5715, \ + CPU_NO_EXTRA2_FUNC, \ + denver_core_pwr_dwn, \ + denver_cluster_pwr_dwn +.endm -declare_cpu_ops_wa denver, DENVER_MIDR_PN1, \ - denver_reset_func, \ - check_errata_cve_2017_5715, \ - CPU_NO_EXTRA2_FUNC, \ - denver_core_pwr_dwn, \ - denver_cluster_pwr_dwn - -declare_cpu_ops_wa denver, DENVER_MIDR_PN2, \ - denver_reset_func, \ - check_errata_cve_2017_5715, \ - CPU_NO_EXTRA2_FUNC, \ - denver_core_pwr_dwn, \ - denver_cluster_pwr_dwn - -declare_cpu_ops_wa denver, DENVER_MIDR_PN3, \ - denver_reset_func, \ - check_errata_cve_2017_5715, \ - CPU_NO_EXTRA2_FUNC, \ - denver_core_pwr_dwn, \ - denver_cluster_pwr_dwn - -declare_cpu_ops_wa denver, DENVER_MIDR_PN4, \ - denver_reset_func, \ - check_errata_cve_2017_5715, \ - CPU_NO_EXTRA2_FUNC, \ - denver_core_pwr_dwn, \ - denver_cluster_pwr_dwn - -declare_cpu_ops_wa denver, DENVER_MIDR_PN5, \ - denver_reset_func, \ - check_errata_cve_2017_5715, \ - CPU_NO_EXTRA2_FUNC, \ - denver_core_pwr_dwn, \ - denver_cluster_pwr_dwn - -declare_cpu_ops_wa denver, DENVER_MIDR_PN6, \ - denver_reset_func, \ - check_errata_cve_2017_5715, \ - CPU_NO_EXTRA2_FUNC, \ - denver_core_pwr_dwn, \ - denver_cluster_pwr_dwn - -declare_cpu_ops_wa denver, DENVER_MIDR_PN7, \ - denver_reset_func, \ - check_errata_cve_2017_5715, \ - CPU_NO_EXTRA2_FUNC, \ - denver_core_pwr_dwn, \ - denver_cluster_pwr_dwn - -declare_cpu_ops_wa denver, DENVER_MIDR_PN8, \ - denver_reset_func, \ - check_errata_cve_2017_5715, \ - CPU_NO_EXTRA2_FUNC, \ - denver_core_pwr_dwn, \ - denver_cluster_pwr_dwn +denver_cpu_ops_wa DENVER_MIDR_PN0 +denver_cpu_ops_wa DENVER_MIDR_PN1 +denver_cpu_ops_wa DENVER_MIDR_PN2 +denver_cpu_ops_wa DENVER_MIDR_PN3 +denver_cpu_ops_wa DENVER_MIDR_PN4 +denver_cpu_ops_wa DENVER_MIDR_PN5 +denver_cpu_ops_wa DENVER_MIDR_PN6 +denver_cpu_ops_wa DENVER_MIDR_PN7 +denver_cpu_ops_wa DENVER_MIDR_PN8 From c6d25c00420844e77f85bdad18abf9a79234330f Mon Sep 17 00:00:00 2001 From: Hemant Nigam Date: Tue, 17 Dec 2019 14:21:38 -0800 Subject: [PATCH 2/7] lib: cpus: denver: add MIDR PN9 variant This patch introduces support for PN9 variant for some Denver based platforms. Original change by: Hemant Nigam Signed-off-by: Kalyani Chidambaram Vaidyanathan Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3 --- include/lib/cpus/aarch64/denver.h | 1 + lib/cpus/aarch64/denver.S | 1 + 2 files changed, 2 insertions(+) diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h index b665bc799..24b6a870c 100644 --- a/include/lib/cpus/aarch64/denver.h +++ b/include/lib/cpus/aarch64/denver.h @@ -17,6 +17,7 @@ #define DENVER_MIDR_PN6 U(0x4E0F0060) #define DENVER_MIDR_PN7 U(0x4E0F0070) #define DENVER_MIDR_PN8 U(0x4E0F0080) +#define DENVER_MIDR_PN9 U(0x4E0F0090) /* Implementer code in the MIDR register */ #define DENVER_IMPL U(0x4E) diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index 834546bf6..83427b84f 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -372,3 +372,4 @@ denver_cpu_ops_wa DENVER_MIDR_PN5 denver_cpu_ops_wa DENVER_MIDR_PN6 denver_cpu_ops_wa DENVER_MIDR_PN7 denver_cpu_ops_wa DENVER_MIDR_PN8 +denver_cpu_ops_wa DENVER_MIDR_PN9 From 0da7e2dd8edbd122580b10dd6a3e53e8f4fc81b2 Mon Sep 17 00:00:00 2001 From: Kalyani Chidambaram Vaidyanathan Date: Mon, 6 Apr 2020 17:34:37 -0700 Subject: [PATCH 3/7] Tegra: remove ENABLE_SVE_FOR_NS = 0 The SVE CPU extension library reads the id_aa64pfr0_el1 register to check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for pre-8.2 platforms, but this flag can safely be enabled now that the library can enable the feature at runtime. This patch updates the makefile to remove "ENABLE_SVE_FOR_NS = 0" as a result. Change-Id: Ia2a89ac90644f8c0d39b41d321e04458ff6be6e1 Signed-off-by: Kalyani Chidambaram Vaidyanathan --- plat/nvidia/tegra/platform.mk | 3 --- 1 file changed, 3 deletions(-) diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk index abe94e4d2..6ed1cdf0b 100644 --- a/plat/nvidia/tegra/platform.mk +++ b/plat/nvidia/tegra/platform.mk @@ -33,9 +33,6 @@ SEPARATE_CODE_AND_RODATA := 1 # do not use coherent memory USE_COHERENT_MEM := 0 -# do not enable SVE -ENABLE_SVE_FOR_NS := 0 - # enable D-cache early during CPU warmboot WARMBOOT_ENABLE_DCACHE_EARLY := 1 From 3ff448f9a70254152b4debf8a52c5342052f7ebc Mon Sep 17 00:00:00 2001 From: Kalyani Chidambaram Vaidyanathan Date: Mon, 15 Jun 2020 16:48:53 -0700 Subject: [PATCH 4/7] Tegra: add platform specific 'runtime_setup' handler Tegra SoCs would like the flexibility to perform chip specific actions before we complete cold boot. This patch introduces a platform specific 'runtime_setup' handler to provide that flexibility. Change-Id: I13b2489f631f775cae6f92acf51a240cd036ef11 Signed-off-by: Kalyani Chidambaram Vaidyanathan --- plat/nvidia/tegra/common/tegra_bl31_setup.c | 26 ++-------------- plat/nvidia/tegra/include/tegra_private.h | 1 + plat/nvidia/tegra/soc/t132/plat_setup.c | 26 ++++++++++++++++ plat/nvidia/tegra/soc/t186/plat_setup.c | 32 ++++++++++++++++++++ plat/nvidia/tegra/soc/t194/plat_setup.c | 33 +++++++++++++++++++++ plat/nvidia/tegra/soc/t210/plat_setup.c | 25 ++++++++++++++++ 6 files changed, 119 insertions(+), 24 deletions(-) diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c index c8bce052a..cb4886f1a 100644 --- a/plat/nvidia/tegra/common/tegra_bl31_setup.c +++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -253,31 +253,9 @@ void bl31_platform_setup(void) void bl31_plat_runtime_setup(void) { /* - * During cold boot, it is observed that the arbitration - * bit is set in the Memory controller leading to false - * error interrupts in the non-secure world. To avoid - * this, clean the interrupt status register before - * booting into the non-secure world + * Platform specific runtime setup */ - tegra_memctrl_clear_pending_interrupts(); - - /* - * During boot, USB3 and flash media (SDMMC/SATA) devices need - * access to IRAM. Because these clients connect to the MC and - * do not have a direct path to the IRAM, the MC implements AHB - * redirection during boot to allow path to IRAM. In this mode - * accesses to a programmed memory address aperture are directed - * to the AHB bus, allowing access to the IRAM. This mode must be - * disabled before we jump to the non-secure world. - */ - tegra_memctrl_disable_ahb_redirection(); - -#if defined(TEGRA_SMMU0_BASE) - /* - * Verify the integrity of the previously configured SMMU(s) settings - */ - tegra_smmu_verify(); -#endif + plat_runtime_setup(); /* * Add final timestamp before exiting BL31. diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h index f1a4948f9..cc2ad869c 100644 --- a/plat/nvidia/tegra/include/tegra_private.h +++ b/plat/nvidia/tegra/include/tegra_private.h @@ -87,6 +87,7 @@ void plat_early_platform_setup(void); void plat_late_platform_setup(void); void plat_relocate_bl32_image(const image_info_t *bl32_img_info); bool plat_supports_system_suspend(void); +void plat_runtime_setup(void); /* Declarations for plat_secondary.c */ void plat_secondary_setup(void); diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c index 9f9abac7f..49e8b5d88 100644 --- a/plat/nvidia/tegra/soc/t132/plat_setup.c +++ b/plat/nvidia/tegra/soc/t132/plat_setup.c @@ -173,3 +173,29 @@ bool plat_supports_system_suspend(void) { return true; } + +/******************************************************************************* + * Platform specific runtime setup. + ******************************************************************************/ +void plat_runtime_setup(void) +{ + /* + * During cold boot, it is observed that the arbitration + * bit is set in the Memory controller leading to false + * error interrupts in the non-secure world. To avoid + * this, clean the interrupt status register before + * booting into the non-secure world + */ + tegra_memctrl_clear_pending_interrupts(); + + /* + * During boot, USB3 and flash media (SDMMC/SATA) devices need + * access to IRAM. Because these clients connect to the MC and + * do not have a direct path to the IRAM, the MC implements AHB + * redirection during boot to allow path to IRAM. In this mode + * accesses to a programmed memory address aperture are directed + * to the AHB bus, allowing access to the IRAM. This mode must be + * disabled before we jump to the non-secure world. + */ + tegra_memctrl_disable_ahb_redirection(); +} diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c index ab374a4e0..d6d090aba 100644 --- a/plat/nvidia/tegra/soc/t186/plat_setup.c +++ b/plat/nvidia/tegra/soc/t186/plat_setup.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -363,3 +364,34 @@ bool plat_supports_system_suspend(void) { return true; } +/******************************************************************************* + * Platform specific runtime setup. + ******************************************************************************/ +void plat_runtime_setup(void) +{ + /* + * During cold boot, it is observed that the arbitration + * bit is set in the Memory controller leading to false + * error interrupts in the non-secure world. To avoid + * this, clean the interrupt status register before + * booting into the non-secure world + */ + tegra_memctrl_clear_pending_interrupts(); + + /* + * During boot, USB3 and flash media (SDMMC/SATA) devices need + * access to IRAM. Because these clients connect to the MC and + * do not have a direct path to the IRAM, the MC implements AHB + * redirection during boot to allow path to IRAM. In this mode + * accesses to a programmed memory address aperture are directed + * to the AHB bus, allowing access to the IRAM. This mode must be + * disabled before we jump to the non-secure world. + */ + tegra_memctrl_disable_ahb_redirection(); + + /* + * Verify the integrity of the previously configured SMMU(s) + * settings + */ + tegra_smmu_verify(); +} diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 1998e9c60..8f7d1e9a1 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -20,7 +20,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -414,3 +416,34 @@ bool plat_supports_system_suspend(void) { return true; } + +/******************************************************************************* + * Platform specific runtime setup. + ******************************************************************************/ +void plat_runtime_setup(void) +{ + /* + * During cold boot, it is observed that the arbitration + * bit is set in the Memory controller leading to false + * error interrupts in the non-secure world. To avoid + * this, clean the interrupt status register before + * booting into the non-secure world + */ + tegra_memctrl_clear_pending_interrupts(); + + /* + * During boot, USB3 and flash media (SDMMC/SATA) devices need + * access to IRAM. Because these clients connect to the MC and + * do not have a direct path to the IRAM, the MC implements AHB + * redirection during boot to allow path to IRAM. In this mode + * accesses to a programmed memory address aperture are directed + * to the AHB bus, allowing access to the IRAM. This mode must be + * disabled before we jump to the non-secure world. + */ + tegra_memctrl_disable_ahb_redirection(); + + /* + * Verify the integrity of the previously configured SMMU(s) settings + */ + tegra_smmu_verify(); +} diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c index 20dde3b9c..68cd38ec3 100644 --- a/plat/nvidia/tegra/soc/t210/plat_setup.c +++ b/plat/nvidia/tegra/soc/t210/plat_setup.c @@ -291,3 +291,28 @@ bool plat_supports_system_suspend(void) return false; } } +/******************************************************************************* + * Platform specific runtime setup. + ******************************************************************************/ +void plat_runtime_setup(void) +{ + /* + * During cold boot, it is observed that the arbitration + * bit is set in the Memory controller leading to false + * error interrupts in the non-secure world. To avoid + * this, clean the interrupt status register before + * booting into the non-secure world + */ + tegra_memctrl_clear_pending_interrupts(); + + /* + * During boot, USB3 and flash media (SDMMC/SATA) devices need + * access to IRAM. Because these clients connect to the MC and + * do not have a direct path to the IRAM, the MC implements AHB + * redirection during boot to allow path to IRAM. In this mode + * accesses to a programmed memory address aperture are directed + * to the AHB bus, allowing access to the IRAM. This mode must be + * disabled before we jump to the non-secure world. + */ + tegra_memctrl_disable_ahb_redirection(); +} From 923c221b6d94c16678abca04ab76b633b052b585 Mon Sep 17 00:00:00 2001 From: anzhou Date: Fri, 26 Jun 2020 15:21:10 +0800 Subject: [PATCH 5/7] Tegra: fixup CNTPS_TVAL_EL1 delay timer reads The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical, decrementing timer as the source. The current logic incorrectly marks this as an incrementing timer, by negating the timer value. This patch fixes the anomaly and updates the driver to remove this logic. Signed-off-by: anzhou Change-Id: I60490bdcaf0b66bf4553a6de3f4e4e32109017f4 --- plat/nvidia/tegra/common/tegra_delay_timer.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/plat/nvidia/tegra/common/tegra_delay_timer.c b/plat/nvidia/tegra/common/tegra_delay_timer.c index cfd9a15e3..d9547c4a3 100644 --- a/plat/nvidia/tegra/common/tegra_delay_timer.c +++ b/plat/nvidia/tegra/common/tegra_delay_timer.c @@ -22,11 +22,9 @@ static uint32_t tegra_timer_get_value(void) /* * Generic delay timer implementation expects the timer to be a down - * counter. We apply bitwise NOT operator to the tick values returned - * by read_cntps_tval_el1() to simulate the down counter. The value is - * clipped from 64 to 32 bits. + * counter. The value is clipped from 64 to 32 bits. */ - return (uint32_t)(~read_cntps_tval_el1()); + return (uint32_t)(read_cntps_tval_el1()); } /* From 26c22a5e3368157fae6c4e905d3779b445e41cc5 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 23 Jul 2020 10:31:42 -0700 Subject: [PATCH 6/7] Tegra186: sanity check power state type This patch sanity checks the power state type before use, from the platform's PSCI handler. Verified with TFTF Standard Test Suite. Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124 Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t186/plat_psci_handlers.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c index 6f58427b3..af4182e24 100644 --- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c @@ -72,6 +72,11 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state, case PSTATE_ID_CORE_IDLE: case PSTATE_ID_CORE_POWERDN: + if (psci_get_pstate_type(power_state) != PSTATE_TYPE_POWERDOWN) { + ret = PSCI_E_INVALID_PARAMS; + break; + } + /* Core powerdown request */ req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; From 5a22eb421d30093a44ca8ef04325ebb9c2472ca3 Mon Sep 17 00:00:00 2001 From: anzhou Date: Tue, 21 Jul 2020 16:22:44 +0800 Subject: [PATCH 7/7] Tegra: platform specific BL31_SIZE This patch moves the BL31_SIZE to the Tegra SoC specific tegra_def.h. This helps newer platforms configure the size of the memory available for BL31. Signed-off-by: anzhou Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82 --- plat/nvidia/tegra/include/platform_def.h | 1 - plat/nvidia/tegra/include/t132/tegra_def.h | 5 +++++ plat/nvidia/tegra/include/t186/tegra_def.h | 5 +++++ plat/nvidia/tegra/include/t194/tegra_def.h | 5 +++++ plat/nvidia/tegra/include/t210/tegra_def.h | 5 +++++ 5 files changed, 20 insertions(+), 1 deletion(-) diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index 2331869d2..2bfd79782 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -66,7 +66,6 @@ /******************************************************************************* * BL31 specific defines. ******************************************************************************/ -#define BL31_SIZE U(0x40000) #define BL31_BASE TZDRAM_BASE #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h index afdcd3691..6b87655e3 100644 --- a/plat/nvidia/tegra/include/t132/tegra_def.h +++ b/plat/nvidia/tegra/include/t132/tegra_def.h @@ -10,6 +10,11 @@ #include +/******************************************************************************* + * Platform BL31 specific defines. + ******************************************************************************/ +#define BL31_SIZE U(0x40000) + /******************************************************************************* * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` * call as the `state-id` field in the 'power state' parameter. diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index 33b21021b..a971cec93 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -10,6 +10,11 @@ #include +/******************************************************************************* + * Platform BL31 specific defines. + ******************************************************************************/ +#define BL31_SIZE U(0x40000) + /******************************************************************************* * MCE apertures used by the ARI interface * diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h index 2d8b88c93..abe193fcd 100644 --- a/plat/nvidia/tegra/include/t194/tegra_def.h +++ b/plat/nvidia/tegra/include/t194/tegra_def.h @@ -9,6 +9,11 @@ #include +/******************************************************************************* + * Platform BL31 specific defines. + ******************************************************************************/ +#define BL31_SIZE U(0x40000) + /******************************************************************************* * Chip specific cluster and cpu numbers ******************************************************************************/ diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index 32fcb4bd8..81b25e036 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -10,6 +10,11 @@ #include +/******************************************************************************* + * Platform BL31 specific defines. + ******************************************************************************/ +#define BL31_SIZE U(0x40000) + /******************************************************************************* * Power down state IDs ******************************************************************************/