From d374060abe9b63296f63f1e3c811aeeddb7a093c Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Thu, 21 Oct 2021 15:28:37 +0800 Subject: [PATCH] feat(nxp/common/rcpm): add RCPM2 registers definition Added some RCPM2 register offset definiton for register: IPSTPCR, IPSTPACKR and POWMGTDCR, also added OVRD bit definiton of register POWMGTDCR. Signed-off-by: Jiafei Pan Change-Id: I301bc1401e053c2089b5eb3672c6e649c805a2ab --- .../default/ch_2/soc_default_helper_macros.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h b/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h index 84f07e635..928ac0512 100644 --- a/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h +++ b/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h @@ -56,6 +56,23 @@ #define RCPM_POWMGTCSR_OFFSET 0x130 #define RCPM_IPPDEXPCR0_OFFSET 0x140 #define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 + +#define RCPM2_IPSTPCR0_OFFSET 0x8 +#define RCPM2_IPSTPCR1_OFFSET 0xC +#define RCPM2_IPSTPCR2_OFFSET 0x10 +#define RCPM2_IPSTPCR3_OFFSET 0x14 +#define RCPM2_IPSTPCR4_OFFSET 0x28 + +#define RCPM2_IPSTPACKR0_OFFSET 0x18 +#define RCPM2_IPSTPACKR1_OFFSET 0x1C +#define RCPM2_IPSTPACKR2_OFFSET 0x20 +#define RCPM2_IPSTPACKR3_OFFSET 0x24 +#define RCPM2_IPSTPACKR4_OFFSET 0x2C +#define RCPM2_POWMGTDCR_OFFSET 0x0 + +/* bitfield masks */ +#define POWMGTDCR_OVRD_EN 0x80000000 + #endif /* NXP_RCPM_ADDR */ #define DCFG_SBEESR2_ADDR 0x20140534