zynqmp: pm: Reimplement clock disable EEMI API
Clock disable EEMI API is reimplemented to use system-level clock and pll EEMI APIs rather than direct MMIO read/write accesses to clock and pll control registers. Since linux still uses clock disable API to reset the PLL in the implementation of pm_clock_disable() we need to workaround this by distinguishing two cases: 1) if the given clock ID corresponds to a PLL output clock ID; or 2) given clock ID is truly an on-chip clock that can be gated. For case 1) we'll call pm_api_clock_pll_disable() implemented in pm_api_clock.h/c. This function will reset the PLL using the system-level PLL set mode EEMI API with the reset mode argument. For case 2) we'll call the PMU to configure the clock gate. This is done using system-level clock disable EEMI API. Functions that appear to be unused after this change is made are removed. Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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@ -2626,58 +2626,6 @@ pm_api_pll_bypass_and_reset(unsigned int clock_id, unsigned int flag)
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return ret;
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return ret;
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}
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}
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/**
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* pm_api_clk_enable_disable() - Enable/Disable the clock for given id
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* @clock_id: Id of the clock to be enabled
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* @enable: Enable(1)/Disable(0)
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*
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* This function is to enable/disable the clock which is not PLL.
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*
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* Return: Returns status, either success or error+reason.
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*/
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static enum pm_ret_status pm_api_clk_enable_disable(unsigned int clock_id,
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unsigned int enable)
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{
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enum pm_ret_status ret = PM_RET_SUCCESS;
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struct pm_clock_node *nodes = *clocks[clock_id].nodes;
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uint8_t num_nodes = clocks[clock_id].num_nodes;
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unsigned int reg, val;
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uint8_t i = 0;
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uint8_t offset = NA_SHIFT, width = NA_WIDTH;
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if (clock_id == CLK_GEM0_TX || clock_id == CLK_GEM1_TX ||
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clock_id == CLK_GEM2_TX || clock_id == CLK_GEM3_TX)
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reg = clocks[clock_id].status_reg;
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else
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reg = clocks[clock_id].control_reg;
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for (i = 0; i < num_nodes; i++) {
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if (nodes->type == TYPE_GATE) {
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offset = nodes->offset;
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width = nodes->width;
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break;
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}
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nodes++;
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}
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if (width == NA_WIDTH)
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return PM_RET_ERROR_NOTSUPPORTED;
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ret = pm_mmio_read(reg, &val);
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if (ret != PM_RET_SUCCESS)
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return ret;
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if ((val & BIT_MASK(offset, width)) == enable)
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return PM_RET_SUCCESS;
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if (enable == 0)
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val &= ~(BIT_MASK(offset, width));
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else
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val |= BIT_MASK(offset, width);
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ret = pm_mmio_write(reg, BIT_MASK(offset, width), val);
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return ret;
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}
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/**
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/**
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* pm_clock_pll_enable() - "Enable" the PLL clock (lock the PLL)
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* pm_clock_pll_enable() - "Enable" the PLL clock (lock the PLL)
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* @pll: PLL to be locked
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* @pll: PLL to be locked
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@ -2700,33 +2648,20 @@ enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll)
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}
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}
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/**
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/**
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* pm_api_clock_disable - Disable the clock for given id
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* pm_clock_pll_disable - "Disable" the PLL clock (bypass/reset the PLL)
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* @clock_id Id of the clock to be disable
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* @pll PLL to be bypassed/reset
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*
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*
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* This function is used by master to disable the clock
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* This function is used to map IOCTL/linux-based PLL handling to system-level
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* including peripherals and PLL clocks.
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* EEMI APIs
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*
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*
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* Return: Returns status, either success or error+reason.
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* Return: Error if the argument is not valid or status as returned by PMU
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*/
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*/
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enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll)
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enum pm_ret_status pm_api_clock_disable(unsigned int clock_id)
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{
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{
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enum pm_ret_status ret = PM_RET_SUCCESS;
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if (!pll)
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if (!pm_clock_valid(clock_id))
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return PM_RET_ERROR_ARGS;
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return PM_RET_ERROR_ARGS;
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if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT)
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return pm_pll_set_mode(pll->nid, PM_PLL_MODE_RESET);
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return PM_RET_ERROR_NOTSUPPORTED;
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/*
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* PLL type clock should not be disabled explicitly.
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* It is done by PMUFW if required.
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*/
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if (!ISPLL(clock_id))
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ret = pm_api_clk_enable_disable(clock_id, 0);
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return ret;
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}
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}
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/**
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/**
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@ -296,7 +296,7 @@ enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id,
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enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id);
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enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id);
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enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll);
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enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll);
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enum pm_ret_status pm_api_clock_disable(unsigned int clock_id);
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enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll);
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enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id,
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enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id,
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unsigned int *state);
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unsigned int *state);
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enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id,
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enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id,
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@ -903,12 +903,20 @@ enum pm_ret_status pm_clock_enable(unsigned int clock_id)
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* This function is used by master to disable the clock
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* This function is used by master to disable the clock
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* including peripherals and PLL clocks.
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* including peripherals and PLL clocks.
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*
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*
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* Return: Returns status, either success or error+reason.
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* @return: Error if an argument is not valid or status as returned by the
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* pm_clock_gate
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*/
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*/
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enum pm_ret_status pm_clock_disable(unsigned int clock_id)
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enum pm_ret_status pm_clock_disable(unsigned int clock_id)
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{
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{
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return pm_api_clock_disable(clock_id);
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struct pm_pll *pll;
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/* First try to handle it as a PLL */
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pll = pm_clock_get_pll(clock_id);
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if (pll)
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return pm_clock_pll_disable(pll);
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/* It's an on-chip clock, PMU should configure clock's gate */
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return pm_clock_gate(clock_id, 0);
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}
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}
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/**
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/**
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