Merge "FVP: Fix BL31 load address and image size for RESET_TO_BL31=1" into integration
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commit
d3b1bfc10f
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@ -277,15 +277,15 @@ And the FVP binary can be run with the following command:
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-C cluster0.NUM_CORES=4 \
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-C cluster0.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cache_state_modelled=1 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.RVBAR=0x04020000 \
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-C cluster0.cpu0.RVBAR=0x04001000 \
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-C cluster0.cpu1.RVBAR=0x04020000 \
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-C cluster0.cpu1.RVBAR=0x04001000 \
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-C cluster0.cpu2.RVBAR=0x04020000 \
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-C cluster0.cpu2.RVBAR=0x04001000 \
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-C cluster0.cpu3.RVBAR=0x04020000 \
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-C cluster0.cpu3.RVBAR=0x04001000 \
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-C cluster1.cpu0.RVBAR=0x04020000 \
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-C cluster1.cpu0.RVBAR=0x04001000 \
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-C cluster1.cpu1.RVBAR=0x04020000 \
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-C cluster1.cpu1.RVBAR=0x04001000 \
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-C cluster1.cpu2.RVBAR=0x04020000 \
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-C cluster1.cpu2.RVBAR=0x04001000 \
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-C cluster1.cpu3.RVBAR=0x04020000 \
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-C cluster1.cpu3.RVBAR=0x04001000 \
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--data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
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--data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \
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--data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
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--data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
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--data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
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@ -116,12 +116,18 @@
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# define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION)
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# define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION)
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#endif
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#endif
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#if RESET_TO_BL31
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/* Size of Trusted SRAM - the first 4KB of shared memory */
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#define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
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ARM_SHARED_RAM_SIZE)
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#else
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/*
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/*
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* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
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* Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
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* calculated using the current BL31 PROGBITS debug size plus the sizes of
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* calculated using the current BL31 PROGBITS debug size plus the sizes of
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* BL2 and BL1-RW
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* BL2 and BL1-RW
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*/
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*/
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#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
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#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
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#endif /* RESET_TO_BL31 */
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#ifndef __aarch64__
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#ifndef __aarch64__
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/*
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/*
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