From d3f70af6e09d669da9c7d7890b7af5a0cdc4b3a5 Mon Sep 17 00:00:00 2001 From: Soby Mathew Date: Thu, 14 Aug 2014 13:36:41 +0100 Subject: [PATCH] Add CPU specific crash reporting handlers This patch adds handlers for dumping Cortex-A57 and Cortex-A53 specific register state to the CPU specific operations framework. The contents of CPUECTLR_EL1 are dumped currently. Change-Id: I63d3dbfc4ac52fef5e25a8cf6b937c6f0975c8ab --- bl31/aarch64/crash_reporting.S | 21 +++------------------ include/lib/aarch64/arch.h | 8 -------- include/lib/cpus/aarch64/cortex_a53.h | 2 ++ include/lib/cpus/aarch64/cortex_a57.h | 2 ++ include/lib/cpus/aarch64/cpu_macros.S | 7 +++++++ lib/cpus/aarch64/aem_generic.S | 13 +++++++++++++ lib/cpus/aarch64/cortex_a53.S | 18 ++++++++++++++++++ lib/cpus/aarch64/cortex_a57.S | 19 +++++++++++++++++++ lib/cpus/aarch64/cpu_helpers.S | 24 ++++++++++++++++++++++++ 9 files changed, 88 insertions(+), 26 deletions(-) diff --git a/bl31/aarch64/crash_reporting.S b/bl31/aarch64/crash_reporting.S index e69878b27..68fe2567a 100644 --- a/bl31/aarch64/crash_reporting.S +++ b/bl31/aarch64/crash_reporting.S @@ -52,9 +52,6 @@ print_spacer: .asciz " =\t\t0x" -cpu_ectlr_reg: - .asciz "cpuectlr_el1 =\t\t0x" - gp_regs: .asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",\ @@ -337,21 +334,9 @@ func do_crash_reporting mrs x10, sp_el0 bl str_in_crash_buf_print - /* Print the CPUECTLR_EL1 reg */ - mrs x0, midr_el1 - lsr x0, x0, #MIDR_PN_SHIFT - and x0, x0, #MIDR_PN_MASK - cmp x0, #MIDR_PN_A57 - b.eq 1f - cmp x0, #MIDR_PN_A53 - b.ne 2f -1: - adr x4, cpu_ectlr_reg - bl asm_print_str - mrs x4, CPUECTLR_EL1 - bl asm_print_hex - bl print_newline -2: + /* Get the cpu specific registers to report */ + bl do_cpu_reg_dump + bl str_in_crash_buf_print /* Print the gic registers */ plat_print_gic_regs diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index 333dcf1d6..97242ccbf 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -39,9 +39,6 @@ #define MIDR_IMPL_SHIFT 0x18 #define MIDR_PN_MASK 0xfff #define MIDR_PN_SHIFT 0x4 -#define MIDR_PN_AEM 0xd0f -#define MIDR_PN_A57 0xd07 -#define MIDR_PN_A53 0xd03 /******************************************************************************* * MPIDR macros @@ -76,11 +73,6 @@ #define ICC_CTLR_EL3 S3_6_C12_C12_4 #define ICC_PMR_EL1 S3_0_C4_C6_0 -/******************************************************************************* - * Implementation defined sysreg encodings - ******************************************************************************/ -#define CPUECTLR_EL1 S3_1_C15_C2_1 - /******************************************************************************* * Generic timer memory mapped registers & offsets ******************************************************************************/ diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index dcae411ea..14821ab68 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -37,6 +37,8 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + #define CPUECTLR_SMP_BIT (1 << 6) #endif /* __CORTEX_A53_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index cf887d009..dc0e0f4ea 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -37,6 +37,8 @@ /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + #define CPUECTLR_SMP_BIT (1 << 6) #define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) #define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index abe8973fc..65fb82d64 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -50,6 +50,10 @@ CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */ CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */ .space 8 #endif +#if (IMAGE_BL31 && CRASH_REPORTING) +CPU_REG_DUMP: /* cpu specific register dump for crash reporting */ + .space 8 +#endif CPU_OPS_SIZE = . /* @@ -71,5 +75,8 @@ CPU_OPS_SIZE = . #if IMAGE_BL31 .quad \_name\()_core_pwr_dwn .quad \_name\()_cluster_pwr_dwn +#endif +#if (IMAGE_BL31 && CRASH_REPORTING) + .quad \_name\()_cpu_reg_dump #endif .endm diff --git a/lib/cpus/aarch64/aem_generic.S b/lib/cpus/aarch64/aem_generic.S index 19c943367..58a64a6c6 100644 --- a/lib/cpus/aarch64/aem_generic.S +++ b/lib/cpus/aarch64/aem_generic.S @@ -68,6 +68,19 @@ func aem_generic_cluster_pwr_dwn mov x0, #DCCISW b dcsw_op_all + /* --------------------------------------------- + * This function provides cpu specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +func aem_generic_cpu_reg_dump + mov x6, #0 /* no registers to report */ + ret + /* cpu_ops for Base AEM FVP */ declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1 diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 08cc9381e..722ce7afb 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -119,4 +119,22 @@ func cortex_a53_cluster_pwr_dwn mov x30, x18 b cortex_a53_disable_smp + /* --------------------------------------------- + * This function provides cortex_a53 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a53_regs, "aS" +cortex_a53_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a53_cpu_reg_dump + adr x6, cortex_a53_regs + mrs x8, CPUECTLR_EL1 + ret + declare_cpu_ops cortex_a53, CORTEX_A53_MIDR diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S index 8de7fe921..8b788566d 100644 --- a/lib/cpus/aarch64/cortex_a57.S +++ b/lib/cpus/aarch64/cortex_a57.S @@ -167,4 +167,23 @@ func cortex_a57_cluster_pwr_dwn mov x30, x18 b cortex_a57_disable_ext_debug + /* --------------------------------------------- + * This function provides cortex_a57 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a57_regs, "aS" +cortex_a57_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a57_cpu_reg_dump + adr x6, cortex_a57_regs + mrs x8, CPUECTLR_EL1 + ret + + declare_cpu_ops cortex_a57, CORTEX_A57_MIDR diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 624a4597d..46584b3f7 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -125,6 +125,30 @@ func init_cpu_ops ret #endif /* IMAGE_BL31 */ +#if IMAGE_BL31 && CRASH_REPORTING + /* + * The cpu specific registers which need to be reported in a crash + * are reported via cpu_ops cpu_reg_dump function. After a matching + * cpu_ops structure entry is found, the correponding cpu_reg_dump + * in the cpu_ops is invoked. + */ + .globl do_cpu_reg_dump +func do_cpu_reg_dump + mov x16, x30 + + /* Get the matching cpu_ops pointer */ + bl get_cpu_ops_ptr + cbz x0, 1f + + /* Get the cpu_ops cpu_reg_dump */ + ldr x2, [x0, #CPU_REG_DUMP] + cbz x2, 1f + blr x2 +1: + mov x30, x16 + ret +#endif + /* * The below function returns the cpu_ops structure matching the * midr of the core. It reads the MIDR_EL1 and finds the matching