feat(plat/mediatek/mt8195): add vcore-dvfs support
Add DVFSRC init flow. Change-Id: Ic5fc78c91359abc12c0f54b01860a7cbe41f3358 Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
This commit is contained in:
Dawei Chien
Rex-BC Chen
parent
3c8d282b22
commit
d562130ea9
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@ -30,7 +30,8 @@ PLAT_SPM_SOURCE_FILES += \
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${CUR_SPM_FOLDER}/constraints/mt_spm_rc_syspll.c \
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${CUR_SPM_FOLDER}/mt_spm_cond.c \
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${CUR_SPM_FOLDER}/mt_spm_suspend.c \
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${CUR_SPM_FOLDER}/mt_spm_idle.c
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${CUR_SPM_FOLDER}/mt_spm_idle.c \
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${CUR_SPM_FOLDER}/mt_spm_vcorefs.c
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ifeq (${MT_SPM_FEATURE_SUPPORT}, no)
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PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_UNSUPPORT
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@ -0,0 +1,522 @@
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/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stddef.h>
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#include <string.h>
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#include <common/debug.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include <mt_spm.h>
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#include <mt_spm_internal.h>
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#include <mt_spm_pmic_wrap.h>
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#include <mt_spm_reg.h>
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#include <mt_spm_vcorefs.h>
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#include <mtk_plat_common.h>
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#include <mtk_sip_svc.h>
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#include <platform_def.h>
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#define VCORE_MAX_OPP 4
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#define DRAM_MAX_OPP 7
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static bool spm_dvfs_init_done;
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static bool dvfs_enable_done;
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static int vcore_opp_0_uv = 750000;
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static int vcore_opp_1_uv = 650000;
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static int vcore_opp_2_uv = 600000;
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static int vcore_opp_3_uv = 550000;
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static struct reg_config dvfsrc_init_configs[] = {
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{ DVFSRC_HRT_REQ_UNIT, 0x0000001E },
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{ DVFSRC_DEBOUNCE_TIME, 0x19651965 },
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{ DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 },
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{ DVFSRC_LEVEL_MASK, 0x000EE000 },
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{ DVFSRC_DDR_QOS0, 0x00000019 },
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{ DVFSRC_DDR_QOS1, 0x00000026 },
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{ DVFSRC_DDR_QOS2, 0x00000033 },
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{ DVFSRC_DDR_QOS3, 0x0000003B },
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{ DVFSRC_DDR_QOS4, 0x0000004C },
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{ DVFSRC_DDR_QOS5, 0x00000066 },
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{ DVFSRC_DDR_QOS6, 0x00660066 },
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{ DVFSRC_LEVEL_LABEL_0_1, 0x50436053 },
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{ DVFSRC_LEVEL_LABEL_2_3, 0x40335042 },
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{ DVFSRC_LEVEL_LABEL_4_5, 0x40314032 },
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{ DVFSRC_LEVEL_LABEL_6_7, 0x30223023 },
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{ DVFSRC_LEVEL_LABEL_8_9, 0x20133021 },
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{ DVFSRC_LEVEL_LABEL_10_11, 0x20112012 },
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{ DVFSRC_LEVEL_LABEL_12_13, 0x10032010 },
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{ DVFSRC_LEVEL_LABEL_14_15, 0x10011002 },
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{ DVFSRC_LEVEL_LABEL_16_17, 0x00131000 },
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{ DVFSRC_LEVEL_LABEL_18_19, 0x00110012 },
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{ DVFSRC_LEVEL_LABEL_20_21, 0x00000010 },
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{ DVFSRC_MD_LATENCY_IMPROVE, 0x00000040 },
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{ DVFSRC_DDR_REQUEST, 0x00004321 },
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{ DVFSRC_DDR_REQUEST3, 0x00000065 },
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{ DVFSRC_DDR_ADD_REQUEST, 0x66543210 },
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{ DVFSRC_HRT_REQUEST, 0x66654321 },
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{ DVFSRC_DDR_REQUEST5, 0x54321000 },
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{ DVFSRC_DDR_REQUEST7, 0x66000000 },
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{ DVFSRC_VCORE_USER_REQ, 0x00010A29 },
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{ DVFSRC_HRT_HIGH_3, 0x18A618A6 },
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{ DVFSRC_HRT_HIGH_2, 0x18A61183 },
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{ DVFSRC_HRT_HIGH_1, 0x0D690B80 },
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{ DVFSRC_HRT_HIGH, 0x070804B0 },
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{ DVFSRC_HRT_LOW_3, 0x18A518A5 },
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{ DVFSRC_HRT_LOW_2, 0x18A51182 },
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{ DVFSRC_HRT_LOW_1, 0x0D680B7F },
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{ DVFSRC_HRT_LOW, 0x070704AF },
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{ DVFSRC_BASIC_CONTROL_3, 0x00000006 },
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{ DVFSRC_INT_EN, 0x00000002 },
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{ DVFSRC_QOS_EN, 0x0000407C },
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{ DVFSRC_HRT_BW_BASE, 0x00000004 },
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{ DVFSRC_PCIE_VCORE_REQ, 0x65908101 },
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{ DVFSRC_CURRENT_FORCE, 0x00000001 },
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{ DVFSRC_BASIC_CONTROL, 0x6698444B },
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{ DVFSRC_BASIC_CONTROL, 0x6698054B },
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{ DVFSRC_CURRENT_FORCE, 0x00000000 },
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};
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static struct pwr_ctrl vcorefs_ctrl = {
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.wake_src = R12_REG_CPU_WAKEUP,
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/* default VCORE DVFS is disabled */
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.pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
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SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS),
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/* SPM_AP_STANDBY_CON */
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/* [0] */
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.reg_wfi_op = 0,
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/* [1] */
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.reg_wfi_type = 0,
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/* [2] */
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.reg_mp0_cputop_idle_mask = 0,
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/* [3] */
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.reg_mp1_cputop_idle_mask = 0,
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/* [4] */
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.reg_mcusys_idle_mask = 0,
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/* [25] */
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.reg_md_apsrc_1_sel = 0,
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/* [26] */
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.reg_md_apsrc_0_sel = 0,
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/* [29] */
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.reg_conn_apsrc_sel = 0,
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/* SPM_SRC_REQ */
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/* [0] */
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.reg_spm_apsrc_req = 0,
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/* [1] */
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.reg_spm_f26m_req = 0,
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/* [3] */
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.reg_spm_infra_req = 0,
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/* [4] */
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.reg_spm_vrf18_req = 0,
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/* [7] FIXME: default disable HW Auto S1*/
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.reg_spm_ddr_en_req = 1,
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/* [8] */
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.reg_spm_dvfs_req = 0,
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/* [9] */
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.reg_spm_sw_mailbox_req = 0,
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/* [10] */
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.reg_spm_sspm_mailbox_req = 0,
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/* [11] */
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.reg_spm_adsp_mailbox_req = 0,
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/* [12] */
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.reg_spm_scp_mailbox_req = 0,
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/* SPM_SRC_MASK */
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/* [0] */
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.reg_sspm_srcclkena_0_mask_b = 1,
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/* [1] */
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.reg_sspm_infra_req_0_mask_b = 1,
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/* [2] */
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.reg_sspm_apsrc_req_0_mask_b = 1,
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/* [3] */
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.reg_sspm_vrf18_req_0_mask_b = 1,
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/* [4] */
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.reg_sspm_ddr_en_0_mask_b = 1,
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/* [5] */
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.reg_scp_srcclkena_mask_b = 1,
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/* [6] */
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.reg_scp_infra_req_mask_b = 1,
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/* [7] */
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.reg_scp_apsrc_req_mask_b = 1,
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/* [8] */
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.reg_scp_vrf18_req_mask_b = 1,
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/* [9] */
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.reg_scp_ddr_en_mask_b = 1,
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/* [10] */
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.reg_audio_dsp_srcclkena_mask_b = 1,
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/* [11] */
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.reg_audio_dsp_infra_req_mask_b = 1,
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/* [12] */
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.reg_audio_dsp_apsrc_req_mask_b = 1,
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/* [13] */
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.reg_audio_dsp_vrf18_req_mask_b = 1,
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/* [14] */
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.reg_audio_dsp_ddr_en_mask_b = 1,
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/* [15] */
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.reg_apu_srcclkena_mask_b = 1,
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/* [16] */
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.reg_apu_infra_req_mask_b = 1,
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/* [17] */
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.reg_apu_apsrc_req_mask_b = 1,
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/* [18] */
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.reg_apu_vrf18_req_mask_b = 1,
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/* [19] */
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.reg_apu_ddr_en_mask_b = 1,
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/* [20] */
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.reg_cpueb_srcclkena_mask_b = 1,
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/* [21] */
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.reg_cpueb_infra_req_mask_b = 1,
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/* [22] */
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.reg_cpueb_apsrc_req_mask_b = 1,
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/* [23] */
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.reg_cpueb_vrf18_req_mask_b = 1,
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/* [24] */
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.reg_cpueb_ddr_en_mask_b = 1,
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/* [25] */
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.reg_bak_psri_srcclkena_mask_b = 0,
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/* [26] */
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.reg_bak_psri_infra_req_mask_b = 0,
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/* [27] */
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.reg_bak_psri_apsrc_req_mask_b = 0,
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/* [28] */
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.reg_bak_psri_vrf18_req_mask_b = 0,
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/* [29] */
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.reg_bak_psri_ddr_en_mask_b = 0,
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/* SPM_SRC2_MASK */
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/* [0] */
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.reg_msdc0_srcclkena_mask_b = 1,
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/* [1] */
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.reg_msdc0_infra_req_mask_b = 1,
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/* [2] */
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.reg_msdc0_apsrc_req_mask_b = 1,
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/* [3] */
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.reg_msdc0_vrf18_req_mask_b = 1,
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/* [4] */
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.reg_msdc0_ddr_en_mask_b = 1,
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/* [5] */
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.reg_msdc1_srcclkena_mask_b = 1,
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/* [6] */
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.reg_msdc1_infra_req_mask_b = 1,
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/* [7] */
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.reg_msdc1_apsrc_req_mask_b = 1,
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/* [8] */
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.reg_msdc1_vrf18_req_mask_b = 1,
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/* [9] */
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.reg_msdc1_ddr_en_mask_b = 1,
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/* [10] */
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.reg_msdc2_srcclkena_mask_b = 1,
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/* [11] */
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.reg_msdc2_infra_req_mask_b = 1,
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/* [12] */
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.reg_msdc2_apsrc_req_mask_b = 1,
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/* [13] */
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.reg_msdc2_vrf18_req_mask_b = 1,
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/* [14] */
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.reg_msdc2_ddr_en_mask_b = 1,
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/* [15] */
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.reg_ufs_srcclkena_mask_b = 1,
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/* [16] */
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.reg_ufs_infra_req_mask_b = 1,
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/* [17] */
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.reg_ufs_apsrc_req_mask_b = 1,
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/* [18] */
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.reg_ufs_vrf18_req_mask_b = 1,
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/* [19] */
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.reg_ufs_ddr_en_mask_b = 1,
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/* [20] */
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.reg_usb_srcclkena_mask_b = 1,
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/* [21] */
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.reg_usb_infra_req_mask_b = 1,
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/* [22] */
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.reg_usb_apsrc_req_mask_b = 1,
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/* [23] */
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.reg_usb_vrf18_req_mask_b = 1,
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/* [24] */
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.reg_usb_ddr_en_mask_b = 1,
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/* [25] */
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.reg_pextp_p0_srcclkena_mask_b = 1,
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/* [26] */
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.reg_pextp_p0_infra_req_mask_b = 1,
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/* [27] */
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.reg_pextp_p0_apsrc_req_mask_b = 1,
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/* [28] */
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.reg_pextp_p0_vrf18_req_mask_b = 1,
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/* [29] */
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.reg_pextp_p0_ddr_en_mask_b = 1,
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/* SPM_SRC3_MASK */
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/* [0] */
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.reg_pextp_p1_srcclkena_mask_b = 1,
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/* [1] */
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.reg_pextp_p1_infra_req_mask_b = 1,
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/* [2] */
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.reg_pextp_p1_apsrc_req_mask_b = 1,
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/* [3] */
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.reg_pextp_p1_vrf18_req_mask_b = 1,
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/* [4] */
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.reg_pextp_p1_ddr_en_mask_b = 1,
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/* [5] */
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.reg_gce0_infra_req_mask_b = 1,
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/* [6] */
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.reg_gce0_apsrc_req_mask_b = 1,
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/* [7] */
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.reg_gce0_vrf18_req_mask_b = 1,
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/* [8] */
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.reg_gce0_ddr_en_mask_b = 1,
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/* [9] */
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.reg_gce1_infra_req_mask_b = 1,
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/* [10] */
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.reg_gce1_apsrc_req_mask_b = 1,
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/* [11] */
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.reg_gce1_vrf18_req_mask_b = 1,
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/* [12] */
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.reg_gce1_ddr_en_mask_b = 1,
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/* [13] */
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.reg_spm_srcclkena_reserved_mask_b = 1,
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/* [14] */
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.reg_spm_infra_req_reserved_mask_b = 1,
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/* [15] */
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.reg_spm_apsrc_req_reserved_mask_b = 1,
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/* [16] */
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.reg_spm_vrf18_req_reserved_mask_b = 1,
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/* [17] */
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.reg_spm_ddr_en_reserved_mask_b = 1,
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/* [18] */
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.reg_disp0_apsrc_req_mask_b = 1,
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/* [19] */
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.reg_disp0_ddr_en_mask_b = 1,
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/* [20] */
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.reg_disp1_apsrc_req_mask_b = 1,
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/* [21] */
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.reg_disp1_ddr_en_mask_b = 1,
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/* [22] */
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.reg_disp2_apsrc_req_mask_b = 1,
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/* [23] */
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.reg_disp2_ddr_en_mask_b = 1,
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/* [24] */
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.reg_disp3_apsrc_req_mask_b = 1,
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/* [25] */
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.reg_disp3_ddr_en_mask_b = 1,
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/* [26] */
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.reg_infrasys_apsrc_req_mask_b = 0,
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/* [27] */
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.reg_infrasys_ddr_en_mask_b = 1,
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/* [28] */
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.reg_cg_check_srcclkena_mask_b = 1,
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/* [29] */
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.reg_cg_check_apsrc_req_mask_b = 1,
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/* [30] */
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.reg_cg_check_vrf18_req_mask_b = 1,
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/* [31] */
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.reg_cg_check_ddr_en_mask_b = 1,
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/* SPM_SRC4_MASK */
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/* [8:0] */
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.reg_mcusys_merge_apsrc_req_mask_b = 0x11,
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/* [17:9] */
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.reg_mcusys_merge_ddr_en_mask_b = 0x11,
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/* [19:18] */
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.reg_dramc_md32_infra_req_mask_b = 0,
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/* [21:20] */
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.reg_dramc_md32_vrf18_req_mask_b = 0,
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/* [23:22] */
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.reg_dramc_md32_ddr_en_mask_b = 0,
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/* [24] */
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.reg_dvfsrc_event_trigger_mask_b = 1,
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/* SPM_WAKEUP_EVENT_MASK2 */
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/* [3:0] */
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.reg_sc_sw2spm_wakeup_mask_b = 0,
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/* [4] */
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.reg_sc_adsp2spm_wakeup_mask_b = 0,
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/* [8:5] */
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.reg_sc_sspm2spm_wakeup_mask_b = 0,
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/* [9] */
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.reg_sc_scp2spm_wakeup_mask_b = 0,
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/* [10] */
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.reg_csyspwrup_ack_mask = 0,
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/* [11] */
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.reg_csyspwrup_req_mask = 1,
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/* SPM_WAKEUP_EVENT_MASK */
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/* [31:0] */
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.reg_wakeup_event_mask = 0xEFFFFFFF,
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/* SPM_WAKEUP_EVENT_EXT_MASK */
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/* [31:0] */
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.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
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};
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struct spm_lp_scen __spm_vcorefs = {
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.pwrctrl = &vcorefs_ctrl,
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};
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static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
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{
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if (cmd < NR_IDX_ALL) {
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mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
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} else {
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INFO("cmd out of range!\n");
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}
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}
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void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
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{
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if (spm_dvfs_init_done == false) {
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mmio_write_32(SPM_DVFS_MISC, (mmio_read_32(SPM_DVFS_MISC) &
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~(SPM_DVFS_FORCE_ENABLE_LSB)) | (SPM_DVFSRC_ENABLE_LSB));
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mmio_write_32(SPM_DVFS_LEVEL, 0x00000001);
|
||||
mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001);
|
||||
|
||||
spm_dvfs_init_done = true;
|
||||
}
|
||||
}
|
||||
|
||||
void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
|
||||
const struct pwr_ctrl *src_pwr_ctrl)
|
||||
{
|
||||
uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
|
||||
SPM_FLAG_DISABLE_VCORE_DFS |
|
||||
SPM_FLAG_ENABLE_VOLTAGE_BIN;
|
||||
|
||||
dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) |
|
||||
(src_pwr_ctrl->pcm_flags & dvfs_mask);
|
||||
|
||||
if (dest_pwr_ctrl->pcm_flags_cust) {
|
||||
dest_pwr_ctrl->pcm_flags_cust = (dest_pwr_ctrl->pcm_flags_cust & (~dvfs_mask)) |
|
||||
(src_pwr_ctrl->pcm_flags & dvfs_mask);
|
||||
}
|
||||
}
|
||||
|
||||
void spm_go_to_vcorefs(uint64_t spm_flags)
|
||||
{
|
||||
__spm_set_power_control(__spm_vcorefs.pwrctrl);
|
||||
__spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
|
||||
__spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
|
||||
__spm_send_cpu_wakeup_event();
|
||||
}
|
||||
|
||||
uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3)
|
||||
{
|
||||
uint64_t ret = 0U;
|
||||
uint64_t cmd = x1;
|
||||
uint64_t spm_flags;
|
||||
|
||||
switch (cmd) {
|
||||
case VCOREFS_SMC_CMD_0:
|
||||
spm_dvfsfw_init(x2, x3);
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_1:
|
||||
spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
|
||||
if (x2 & SPM_FLAG_DISABLE_VCORE_DVS)
|
||||
spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
|
||||
if (x2 & SPM_FLAG_DISABLE_VCORE_DFS)
|
||||
spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
|
||||
spm_go_to_vcorefs(spm_flags);
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_3:
|
||||
spm_vcorefs_pwarp_cmd(x2, x3);
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_2:
|
||||
case VCOREFS_SMC_CMD_4:
|
||||
case VCOREFS_SMC_CMD_5:
|
||||
case VCOREFS_SMC_CMD_7:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void dvfsrc_init(void)
|
||||
{
|
||||
int i;
|
||||
int count = ARRAY_SIZE(dvfsrc_init_configs);
|
||||
|
||||
if (dvfs_enable_done == false) {
|
||||
for (i = 0; i < count; i++) {
|
||||
mmio_write_32(dvfsrc_init_configs[i].offset,
|
||||
dvfsrc_init_configs[i].val);
|
||||
}
|
||||
|
||||
mmio_write_32(DVFSRC_QOS_EN, 0x0011007C);
|
||||
|
||||
dvfs_enable_done = true;
|
||||
}
|
||||
}
|
||||
|
||||
static void spm_vcorefs_vcore_setting(uint64_t flag)
|
||||
{
|
||||
spm_vcorefs_pwarp_cmd(3, __vcore_uv_to_pmic(vcore_opp_3_uv));
|
||||
spm_vcorefs_pwarp_cmd(2, __vcore_uv_to_pmic(vcore_opp_2_uv));
|
||||
spm_vcorefs_pwarp_cmd(1, __vcore_uv_to_pmic(vcore_opp_1_uv));
|
||||
spm_vcorefs_pwarp_cmd(0, __vcore_uv_to_pmic(vcore_opp_0_uv));
|
||||
}
|
||||
|
||||
int spm_vcorefs_get_vcore(unsigned int gear)
|
||||
{
|
||||
int ret_val;
|
||||
|
||||
switch (gear) {
|
||||
case 3:
|
||||
ret_val = vcore_opp_0_uv;
|
||||
case 2:
|
||||
ret_val = vcore_opp_1_uv;
|
||||
case 1:
|
||||
ret_val = vcore_opp_2_uv;
|
||||
case 0:
|
||||
default:
|
||||
ret_val = vcore_opp_3_uv;
|
||||
}
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
uint64_t spm_vcorefs_v2_args(u_register_t x1, u_register_t x2, u_register_t x3, u_register_t *x4)
|
||||
{
|
||||
uint64_t ret = 0U;
|
||||
uint64_t cmd = x1;
|
||||
uint64_t spm_flags;
|
||||
|
||||
switch (cmd) {
|
||||
case VCOREFS_SMC_CMD_INIT:
|
||||
/* vcore_dvfs init + kick */
|
||||
spm_dvfsfw_init(0, 0);
|
||||
spm_vcorefs_vcore_setting(x3 & 0xF);
|
||||
spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
|
||||
if (x2 & 0x1) {
|
||||
spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
|
||||
}
|
||||
if (x2 & 0x2) {
|
||||
spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
|
||||
}
|
||||
spm_go_to_vcorefs(spm_flags);
|
||||
dvfsrc_init();
|
||||
*x4 = 0U;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_OPP_TYPE:
|
||||
/* get dram type */
|
||||
*x4 = 0U;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_FW_TYPE:
|
||||
*x4 = 0U;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_GET_UV:
|
||||
*x4 = spm_vcorefs_get_vcore(x2);
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_GET_NUM_V:
|
||||
*x4 = VCORE_MAX_OPP;
|
||||
break;
|
||||
case VCOREFS_SMC_CMD_GET_NUM_F:
|
||||
*x4 = DRAM_MAX_OPP;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,328 @@
|
|||
/*
|
||||
* Copyright (c) 2021, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#ifndef __MT_SPM_VCOREFS__H__
|
||||
#define __MT_SPM_VCOREFS__H__
|
||||
|
||||
int spm_vcorefs_get_vcore(unsigned int gear);
|
||||
uint64_t spm_vcorefs_v2_args(u_register_t x1, u_register_t x2, u_register_t x3,
|
||||
u_register_t *x4);
|
||||
|
||||
enum vcorefs_smc_cmd {
|
||||
VCOREFS_SMC_CMD_0 = 0,
|
||||
VCOREFS_SMC_CMD_1,
|
||||
VCOREFS_SMC_CMD_2,
|
||||
VCOREFS_SMC_CMD_3,
|
||||
VCOREFS_SMC_CMD_4,
|
||||
/* check spmfw status */
|
||||
VCOREFS_SMC_CMD_5,
|
||||
|
||||
/* get spmfw type */
|
||||
VCOREFS_SMC_CMD_6,
|
||||
|
||||
/* get spm reg status */
|
||||
VCOREFS_SMC_CMD_7,
|
||||
|
||||
NUM_VCOREFS_SMC_CMD,
|
||||
};
|
||||
|
||||
enum vcorefs_smc_cmd_new {
|
||||
VCOREFS_SMC_CMD_INIT = 0,
|
||||
VCOREFS_SMC_CMD_KICK = 1,
|
||||
VCOREFS_SMC_CMD_OPP_TYPE = 2,
|
||||
VCOREFS_SMC_CMD_FW_TYPE = 3,
|
||||
VCOREFS_SMC_CMD_GET_UV = 4,
|
||||
VCOREFS_SMC_CMD_GET_FREQ = 5,
|
||||
VCOREFS_SMC_CMD_GET_NUM_V = 6,
|
||||
VCOREFS_SMC_CMD_GET_NUM_F = 7,
|
||||
VCOREFS_SMC_CMD_FB_ACTION = 8,
|
||||
/*chip specific setting */
|
||||
VCOREFS_SMC_CMD_SET_FREQ = 16,
|
||||
VCOREFS_SMC_CMD_SET_EFUSE = 17,
|
||||
VCOREFS_SMC_CMD_GET_EFUSE = 18,
|
||||
VCOREFS_SMC_CMD_DVFS_HOPPING = 19,
|
||||
VCOREFS_SMC_CMD_DVFS_HOPPING_STATE = 20,
|
||||
};
|
||||
|
||||
enum dvfsrc_channel {
|
||||
DVFSRC_CHANNEL_1 = 1,
|
||||
DVFSRC_CHANNEL_2,
|
||||
DVFSRC_CHANNEL_3,
|
||||
DVFSRC_CHANNEL_4,
|
||||
NUM_DVFSRC_CHANNEL,
|
||||
};
|
||||
|
||||
#define _VCORE_BASE_UV 400000
|
||||
#define _VCORE_STEP_UV 6250
|
||||
|
||||
/* PMIC */
|
||||
#define __vcore_pmic_to_uv(pmic) \
|
||||
(((pmic) * _VCORE_STEP_UV) + _VCORE_BASE_UV)
|
||||
|
||||
#define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \
|
||||
((((uv) - _VCORE_BASE_UV) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV)
|
||||
|
||||
struct reg_config {
|
||||
uint32_t offset;
|
||||
uint32_t val;
|
||||
};
|
||||
|
||||
#define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
|
||||
#define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x4)
|
||||
#define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x8)
|
||||
#define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0xC)
|
||||
#define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x10)
|
||||
#define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
|
||||
#define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x18)
|
||||
#define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x1C)
|
||||
#define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x20)
|
||||
#define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x24)
|
||||
#define DVFSRC_EMI_REQUEST2 (DVFSRC_BASE + 0x28)
|
||||
#define DVFSRC_EMI_REQUEST3 (DVFSRC_BASE + 0x2C)
|
||||
#define DVFSRC_EMI_REQUEST4 (DVFSRC_BASE + 0x30)
|
||||
#define DVFSRC_EMI_REQUEST5 (DVFSRC_BASE + 0x34)
|
||||
#define DVFSRC_EMI_REQUEST6 (DVFSRC_BASE + 0x38)
|
||||
#define DVFSRC_EMI_HRT (DVFSRC_BASE + 0x3C)
|
||||
#define DVFSRC_EMI_HRT2 (DVFSRC_BASE + 0x40)
|
||||
#define DVFSRC_EMI_HRT3 (DVFSRC_BASE + 0x44)
|
||||
#define DVFSRC_EMI_QOS0 (DVFSRC_BASE + 0x48)
|
||||
#define DVFSRC_EMI_QOS1 (DVFSRC_BASE + 0x4C)
|
||||
#define DVFSRC_EMI_QOS2 (DVFSRC_BASE + 0x50)
|
||||
#define DVFSRC_EMI_MD2SPM0 (DVFSRC_BASE + 0x54)
|
||||
#define DVFSRC_EMI_MD2SPM1 (DVFSRC_BASE + 0x58)
|
||||
#define DVFSRC_EMI_MD2SPM2 (DVFSRC_BASE + 0x5C)
|
||||
#define DVFSRC_EMI_MD2SPM0_T (DVFSRC_BASE + 0x60)
|
||||
#define DVFSRC_EMI_MD2SPM1_T (DVFSRC_BASE + 0x64)
|
||||
#define DVFSRC_EMI_MD2SPM2_T (DVFSRC_BASE + 0x68)
|
||||
#define DVFSRC_VCORE_REQUEST (DVFSRC_BASE + 0x6C)
|
||||
#define DVFSRC_VCORE_REQUEST2 (DVFSRC_BASE + 0x70)
|
||||
#define DVFSRC_VCORE_REQUEST3 (DVFSRC_BASE + 0x74)
|
||||
#define DVFSRC_VCORE_REQUEST4 (DVFSRC_BASE + 0x78)
|
||||
#define DVFSRC_VCORE_HRT (DVFSRC_BASE + 0x7C)
|
||||
#define DVFSRC_VCORE_HRT2 (DVFSRC_BASE + 0x80)
|
||||
#define DVFSRC_VCORE_HRT3 (DVFSRC_BASE + 0x84)
|
||||
#define DVFSRC_VCORE_QOS0 (DVFSRC_BASE + 0x88)
|
||||
#define DVFSRC_VCORE_QOS1 (DVFSRC_BASE + 0x8C)
|
||||
#define DVFSRC_VCORE_QOS2 (DVFSRC_BASE + 0x90)
|
||||
#define DVFSRC_VCORE_MD2SPM0 (DVFSRC_BASE + 0x94)
|
||||
#define DVFSRC_VCORE_MD2SPM1 (DVFSRC_BASE + 0x98)
|
||||
#define DVFSRC_VCORE_MD2SPM2 (DVFSRC_BASE + 0x9C)
|
||||
#define DVFSRC_VCORE_MD2SPM0_T (DVFSRC_BASE + 0xA0)
|
||||
#define DVFSRC_VCORE_MD2SPM1_T (DVFSRC_BASE + 0xA4)
|
||||
#define DVFSRC_VCORE_MD2SPM2_T (DVFSRC_BASE + 0xA8)
|
||||
#define DVFSRC_MD_VSRAM_REMAP (DVFSRC_BASE + 0xBC)
|
||||
#define DVFSRC_HALT_SW_CONTROL (DVFSRC_BASE + 0xC0)
|
||||
#define DVFSRC_INT (DVFSRC_BASE + 0xC4)
|
||||
#define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8)
|
||||
#define DVFSRC_INT_CLR (DVFSRC_BASE + 0xCC)
|
||||
#define DVFSRC_BW_MON_WINDOW (DVFSRC_BASE + 0xD0)
|
||||
#define DVFSRC_BW_MON_THRES_1 (DVFSRC_BASE + 0xD4)
|
||||
#define DVFSRC_BW_MON_THRES_2 (DVFSRC_BASE + 0xD8)
|
||||
#define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC)
|
||||
#define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0)
|
||||
#define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4)
|
||||
#define DVFSRC_DEBOUNCE_FOUR (DVFSRC_BASE + 0xF0)
|
||||
#define DVFSRC_DEBOUNCE_RISE_FALL (DVFSRC_BASE + 0xF4)
|
||||
#define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8)
|
||||
#define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100)
|
||||
#define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104)
|
||||
#define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108)
|
||||
#define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C)
|
||||
#define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110)
|
||||
#define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114)
|
||||
#define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118)
|
||||
#define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C)
|
||||
#define DVFSRC_MM_BW_0 (DVFSRC_BASE + 0x200)
|
||||
#define DVFSRC_MM_BW_1 (DVFSRC_BASE + 0x204)
|
||||
#define DVFSRC_MM_BW_2 (DVFSRC_BASE + 0x208)
|
||||
#define DVFSRC_MM_BW_3 (DVFSRC_BASE + 0x20C)
|
||||
#define DVFSRC_MM_BW_4 (DVFSRC_BASE + 0x210)
|
||||
#define DVFSRC_MM_BW_5 (DVFSRC_BASE + 0x214)
|
||||
#define DVFSRC_MM_BW_6 (DVFSRC_BASE + 0x218)
|
||||
#define DVFSRC_MM_BW_7 (DVFSRC_BASE + 0x21C)
|
||||
#define DVFSRC_MM_BW_8 (DVFSRC_BASE + 0x220)
|
||||
#define DVFSRC_MM_BW_9 (DVFSRC_BASE + 0x224)
|
||||
#define DVFSRC_MM_BW_10 (DVFSRC_BASE + 0x228)
|
||||
#define DVFSRC_MM_BW_11 (DVFSRC_BASE + 0x22C)
|
||||
#define DVFSRC_MM_BW_12 (DVFSRC_BASE + 0x230)
|
||||
#define DVFSRC_MM_BW_13 (DVFSRC_BASE + 0x234)
|
||||
#define DVFSRC_MM_BW_14 (DVFSRC_BASE + 0x238)
|
||||
#define DVFSRC_MM_BW_15 (DVFSRC_BASE + 0x23C)
|
||||
#define DVFSRC_MD_BW_0 (DVFSRC_BASE + 0x240)
|
||||
#define DVFSRC_MD_BW_1 (DVFSRC_BASE + 0x244)
|
||||
#define DVFSRC_MD_BW_2 (DVFSRC_BASE + 0x248)
|
||||
#define DVFSRC_MD_BW_3 (DVFSRC_BASE + 0x24C)
|
||||
#define DVFSRC_MD_BW_4 (DVFSRC_BASE + 0x250)
|
||||
#define DVFSRC_MD_BW_5 (DVFSRC_BASE + 0x254)
|
||||
#define DVFSRC_MD_BW_6 (DVFSRC_BASE + 0x258)
|
||||
#define DVFSRC_MD_BW_7 (DVFSRC_BASE + 0x25C)
|
||||
#define DVFSRC_SW_BW_0 (DVFSRC_BASE + 0x260)
|
||||
#define DVFSRC_SW_BW_1 (DVFSRC_BASE + 0x264)
|
||||
#define DVFSRC_SW_BW_2 (DVFSRC_BASE + 0x268)
|
||||
#define DVFSRC_SW_BW_3 (DVFSRC_BASE + 0x26C)
|
||||
#define DVFSRC_SW_BW_4 (DVFSRC_BASE + 0x270)
|
||||
#define DVFSRC_SW_BW_5 (DVFSRC_BASE + 0x274)
|
||||
#define DVFSRC_SW_BW_6 (DVFSRC_BASE + 0x278)
|
||||
#define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280)
|
||||
#define DVFSRC_MD_BW_URG (DVFSRC_BASE + 0x284)
|
||||
#define DVFSRC_ISP_HRT (DVFSRC_BASE + 0x290)
|
||||
#define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294)
|
||||
#define DVFSRC_SEC_SW_REQ (DVFSRC_BASE + 0x304)
|
||||
#define DVFSRC_EMI_MON_DEBOUNCE_TIME (DVFSRC_BASE + 0x308)
|
||||
#define DVFSRC_MD_LATENCY_IMPROVE (DVFSRC_BASE + 0x30C)
|
||||
#define DVFSRC_BASIC_CONTROL_3 (DVFSRC_BASE + 0x310)
|
||||
#define DVFSRC_DEBOUNCE_TIME (DVFSRC_BASE + 0x314)
|
||||
#define DVFSRC_LEVEL_MASK (DVFSRC_BASE + 0x318)
|
||||
#define DVFSRC_DEFAULT_OPP (DVFSRC_BASE + 0x31C)
|
||||
#define DVFSRC_95MD_SCEN_EMI0 (DVFSRC_BASE + 0x500)
|
||||
#define DVFSRC_95MD_SCEN_EMI1 (DVFSRC_BASE + 0x504)
|
||||
#define DVFSRC_95MD_SCEN_EMI2 (DVFSRC_BASE + 0x508)
|
||||
#define DVFSRC_95MD_SCEN_EMI3 (DVFSRC_BASE + 0x50C)
|
||||
#define DVFSRC_95MD_SCEN_EMI0_T (DVFSRC_BASE + 0x510)
|
||||
#define DVFSRC_95MD_SCEN_EMI1_T (DVFSRC_BASE + 0x514)
|
||||
#define DVFSRC_95MD_SCEN_EMI2_T (DVFSRC_BASE + 0x518)
|
||||
#define DVFSRC_95MD_SCEN_EMI3_T (DVFSRC_BASE + 0x51C)
|
||||
#define DVFSRC_95MD_SCEN_EMI4 (DVFSRC_BASE + 0x520)
|
||||
#define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x524)
|
||||
#define DVFSRC_95MD_SCEN_BW1 (DVFSRC_BASE + 0x528)
|
||||
#define DVFSRC_95MD_SCEN_BW2 (DVFSRC_BASE + 0x52C)
|
||||
#define DVFSRC_95MD_SCEN_BW3 (DVFSRC_BASE + 0x530)
|
||||
#define DVFSRC_95MD_SCEN_BW0_T (DVFSRC_BASE + 0x534)
|
||||
#define DVFSRC_95MD_SCEN_BW1_T (DVFSRC_BASE + 0x538)
|
||||
#define DVFSRC_95MD_SCEN_BW2_T (DVFSRC_BASE + 0x53C)
|
||||
#define DVFSRC_95MD_SCEN_BW3_T (DVFSRC_BASE + 0x540)
|
||||
#define DVFSRC_95MD_SCEN_BW4 (DVFSRC_BASE + 0x544)
|
||||
#define DVFSRC_MD_LEVEL_SW_REG (DVFSRC_BASE + 0x548)
|
||||
#define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x600)
|
||||
#define DVFSRC_RSRV_1 (DVFSRC_BASE + 0x604)
|
||||
#define DVFSRC_RSRV_2 (DVFSRC_BASE + 0x608)
|
||||
#define DVFSRC_RSRV_3 (DVFSRC_BASE + 0x60C)
|
||||
#define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610)
|
||||
#define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614)
|
||||
#define DVFSRC_SPM_RESEND (DVFSRC_BASE + 0x630)
|
||||
#define DVFSRC_DEBUG_STA_0 (DVFSRC_BASE + 0x700)
|
||||
#define DVFSRC_DEBUG_STA_1 (DVFSRC_BASE + 0x704)
|
||||
#define DVFSRC_DEBUG_STA_2 (DVFSRC_BASE + 0x708)
|
||||
#define DVFSRC_DEBUG_STA_3 (DVFSRC_BASE + 0x70C)
|
||||
#define DVFSRC_DEBUG_STA_4 (DVFSRC_BASE + 0x710)
|
||||
#define DVFSRC_DEBUG_STA_5 (DVFSRC_BASE + 0x714)
|
||||
#define DVFSRC_EMI_REQUEST7 (DVFSRC_BASE + 0x800)
|
||||
#define DVFSRC_EMI_HRT_1 (DVFSRC_BASE + 0x804)
|
||||
#define DVFSRC_EMI_HRT2_1 (DVFSRC_BASE + 0x808)
|
||||
#define DVFSRC_EMI_HRT3_1 (DVFSRC_BASE + 0x80C)
|
||||
#define DVFSRC_EMI_QOS3 (DVFSRC_BASE + 0x810)
|
||||
#define DVFSRC_EMI_QOS4 (DVFSRC_BASE + 0x814)
|
||||
#define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00)
|
||||
#define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04)
|
||||
#define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08)
|
||||
#define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C)
|
||||
#define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10)
|
||||
#define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14)
|
||||
#define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18)
|
||||
#define DVFSRC_DDR_HRT (DVFSRC_BASE + 0xA1C)
|
||||
#define DVFSRC_DDR_HRT2 (DVFSRC_BASE + 0xA20)
|
||||
#define DVFSRC_DDR_HRT3 (DVFSRC_BASE + 0xA24)
|
||||
#define DVFSRC_DDR_HRT_1 (DVFSRC_BASE + 0xA28)
|
||||
#define DVFSRC_DDR_HRT2_1 (DVFSRC_BASE + 0xA2C)
|
||||
#define DVFSRC_DDR_HRT3_1 (DVFSRC_BASE + 0xA30)
|
||||
#define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34)
|
||||
#define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38)
|
||||
#define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C)
|
||||
#define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40)
|
||||
#define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44)
|
||||
#define DVFSRC_DDR_MD2SPM0 (DVFSRC_BASE + 0xA48)
|
||||
#define DVFSRC_DDR_MD2SPM1 (DVFSRC_BASE + 0xA4C)
|
||||
#define DVFSRC_DDR_MD2SPM2 (DVFSRC_BASE + 0xA50)
|
||||
#define DVFSRC_DDR_MD2SPM0_T (DVFSRC_BASE + 0xA54)
|
||||
#define DVFSRC_DDR_MD2SPM1_T (DVFSRC_BASE + 0xA58)
|
||||
#define DVFSRC_DDR_MD2SPM2_T (DVFSRC_BASE + 0xA5C)
|
||||
#define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60)
|
||||
#define DVSFRC_HRT_REQ_MD_URG (DVFSRC_BASE + 0xA64)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_0 (DVFSRC_BASE + 0xA68)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_1 (DVFSRC_BASE + 0xA6C)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_2 (DVFSRC_BASE + 0xA70)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_3 (DVFSRC_BASE + 0xA74)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_4 (DVFSRC_BASE + 0xA78)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_5 (DVFSRC_BASE + 0xA7C)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_6 (DVFSRC_BASE + 0xA80)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_7 (DVFSRC_BASE + 0xA84)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_0 (DVFSRC_BASE + 0xA88)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_1 (DVFSRC_BASE + 0xA8C)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_2 (DVFSRC_BASE + 0xA90)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_3 (DVFSRC_BASE + 0xA94)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_4 (DVFSRC_BASE + 0xA98)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_5 (DVFSRC_BASE + 0xA9C)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_6 (DVFSRC_BASE + 0xAA0)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_7 (DVFSRC_BASE + 0xAA4)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_8 (DVFSRC_BASE + 0xAA8)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_9 (DVFSRC_BASE + 0xAAC)
|
||||
#define DVFSRC_HRT_REQ_MD_BW_10 (DVFSRC_BASE + 0xAB0)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_8 (DVFSRC_BASE + 0xAB4)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_9 (DVFSRC_BASE + 0xAB8)
|
||||
#define DVFSRC_HRT1_REQ_MD_BW_10 (DVFSRC_BASE + 0xABC)
|
||||
#define DVFSRC_HRT_REQ_BW_SW_REG (DVFSRC_BASE + 0xAC0)
|
||||
#define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4)
|
||||
#define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8)
|
||||
#define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC)
|
||||
#define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0)
|
||||
#define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4)
|
||||
#define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8)
|
||||
#define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC)
|
||||
#define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0)
|
||||
#define DVFSRC_LAST (DVFSRC_BASE + 0xAE4)
|
||||
#define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8)
|
||||
#define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC)
|
||||
#define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0)
|
||||
#define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4)
|
||||
#define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8)
|
||||
#define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC)
|
||||
#define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00)
|
||||
#define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04)
|
||||
#define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08)
|
||||
#define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C)
|
||||
#define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0)
|
||||
#define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4)
|
||||
#define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8)
|
||||
#define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC)
|
||||
#define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00)
|
||||
#define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04)
|
||||
#define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08)
|
||||
#define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C)
|
||||
#define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0)
|
||||
#define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4)
|
||||
#define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8)
|
||||
#define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC)
|
||||
#define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00)
|
||||
#define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04)
|
||||
#define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08)
|
||||
#define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C)
|
||||
#define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10)
|
||||
#define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14)
|
||||
#define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18)
|
||||
#define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C)
|
||||
#define DVFSRC_VCORE_REQUEST5 (DVFSRC_BASE + 0xD20)
|
||||
#define DVFSRC_VCORE_HRT_1 (DVFSRC_BASE + 0xD24)
|
||||
#define DVFSRC_VCORE_HRT2_1 (DVFSRC_BASE + 0xD28)
|
||||
#define DVFSRC_VCORE_HRT3_1 (DVFSRC_BASE + 0xD2C)
|
||||
#define DVFSRC_VCORE_QOS3 (DVFSRC_BASE + 0xD30)
|
||||
#define DVFSRC_VCORE_QOS4 (DVFSRC_BASE + 0xD34)
|
||||
#define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38)
|
||||
#define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C)
|
||||
#define DVFSRC_BASIC_CONTROL_2 (DVFSRC_BASE + 0xD40)
|
||||
#define DVFSRC_CURRENT_LEVEL (DVFSRC_BASE + 0xD44)
|
||||
#define DVFSRC_TARGET_LEVEL (DVFSRC_BASE + 0xD48)
|
||||
#define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C)
|
||||
#define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50)
|
||||
#define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54)
|
||||
#define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58)
|
||||
#define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C)
|
||||
#define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60)
|
||||
#define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64)
|
||||
#define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68)
|
||||
#define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C)
|
||||
#define DVFSRC_TARGET_FORCE (DVFSRC_BASE + 0xD70)
|
||||
#define DVFSRC_EMI_ADD_REQUEST (DVFSRC_BASE + 0xD74)
|
||||
|
||||
#endif /* __MT_SPM_VCOREFS__H__ */
|
||||
|
|
@ -31,6 +31,7 @@
|
|||
#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
|
||||
#define VDOSYS0_BASE (IO_PHYS + 0x0C01A000)
|
||||
#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
|
||||
#define DVFSRC_BASE (IO_PHYS + 0x00012000)
|
||||
|
||||
/*******************************************************************************
|
||||
* DP/eDP related constants
|
||||
|
|
|
|||
|
|
@ -7,6 +7,8 @@
|
|||
#include <common/debug.h>
|
||||
#include <common/runtime_svc.h>
|
||||
#include <mt_dp.h>
|
||||
#include <mt_spm.h>
|
||||
#include <mt_spm_vcorefs.h>
|
||||
#include <mtk_sip_svc.h>
|
||||
#include "plat_sip_calls.h"
|
||||
|
||||
|
|
@ -28,6 +30,11 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
|
|||
ret = dp_secure_handler(x1, x2, &ret_val);
|
||||
SMC_RET2(handle, ret, ret_val);
|
||||
break;
|
||||
case MTK_SIP_VCORE_CONTROL_ARCH32:
|
||||
case MTK_SIP_VCORE_CONTROL_ARCH64:
|
||||
ret = spm_vcorefs_v2_args(x1, x2, x3, &x4);
|
||||
SMC_RET2(handle, ret, x4);
|
||||
break;
|
||||
default:
|
||||
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in New Issue