Tegra186: setup: fix defects flagged by MISRA scan
Main fixes:
Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
Force operands of an operator to the same type category [Rule 10.4]
Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
Change-Id: I4840c3122939f736113d61f1462af3bd7b0b5085
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This commit is contained in:
Anthony Zhou
Varun Wadekar
parent
214e8464ac
commit
d6102295c5
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@ -59,7 +59,7 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
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/* Declarations for plat_setup.c */
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const mmap_region_t *plat_get_mmio_map(void);
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uint32_t plat_get_console_from_id(int id);
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uint32_t plat_get_console_from_id(int32_t id);
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void plat_gic_setup(void);
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struct tegra_bl31_params *plat_get_bl31_params(void);
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plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
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@ -31,8 +31,8 @@
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* Tegra186 CPU numbers in cluster #0
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*******************************************************************************
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*/
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#define TEGRA186_CLUSTER0_CORE2 2
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#define TEGRA186_CLUSTER0_CORE3 3
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#define TEGRA186_CLUSTER0_CORE2 2U
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#define TEGRA186_CLUSTER0_CORE3 3U
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/*******************************************************************************
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* The Tegra power domain tree has a single system level power domain i.e. a
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@ -40,7 +40,7 @@
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* the number of power domains at the highest power level.
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*******************************************************************************
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*/
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const unsigned char tegra_power_domain_tree_desc[] = {
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const uint8_t tegra_power_domain_tree_desc[] = {
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/* No of root nodes */
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1,
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/* No of clusters */
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@ -54,7 +54,7 @@ const unsigned char tegra_power_domain_tree_desc[] = {
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/*******************************************************************************
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* This function returns the Tegra default topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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const uint8_t *plat_get_power_domain_tree_desc(void)
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{
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return tegra_power_domain_tree_desc;
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}
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@ -63,41 +63,41 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
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* Table of regions to map using the MMU.
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*/
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static const mmap_region_t tegra_mmap[] = {
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MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
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MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/
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MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */
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MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */
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MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
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MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
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MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
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MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */
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MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000U, /* 128KB - ARM/Denver */
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
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MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
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MT_DEVICE | MT_RW | MT_SECURE),
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{0}
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};
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@ -114,7 +114,7 @@ const mmap_region_t *plat_get_mmio_map(void)
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/*******************************************************************************
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* Handler to get the System Counter Frequency
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******************************************************************************/
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unsigned int plat_get_syscnt_freq2(void)
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uint32_t plat_get_syscnt_freq2(void)
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{
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return 31250000;
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}
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@ -141,12 +141,17 @@ static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
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/*******************************************************************************
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* Retrieve the UART controller base to be used as the console
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******************************************************************************/
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uint32_t plat_get_console_from_id(int id)
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uint32_t plat_get_console_from_id(int32_t id)
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{
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if (id > TEGRA186_MAX_UART_PORTS)
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return 0;
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uint32_t ret;
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return tegra186_uart_addresses[id];
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if (id > TEGRA186_MAX_UART_PORTS) {
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ret = 0;
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} else {
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ret = tegra186_uart_addresses[id];
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}
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return ret;
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}
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/*******************************************************************************
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@ -170,7 +175,7 @@ void plat_early_platform_setup(void)
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(impl != (uint64_t)DENVER_IMPL)) {
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val = read_l2ctlr_el1();
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val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
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val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
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write_l2ctlr_el1(val);
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}
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}
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@ -194,8 +199,9 @@ void plat_gic_setup(void)
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* Initialize the FIQ handler only if the platform supports any
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* FIQ interrupt sources.
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*/
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if (sizeof(tegra186_interrupt_props) > 0)
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if (sizeof(tegra186_interrupt_props) > 0U) {
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tegra_fiq_handler_setup();
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}
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}
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/*******************************************************************************
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@ -228,33 +234,34 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cluster_id, cpu_id, pos;
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u_register_t cluster_id, cpu_id, pos;
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int32_t ret;
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cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
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cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
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/*
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* Validate cluster_id by checking whether it represents
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* one of the two clusters present on the platform.
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*/
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if (cluster_id >= PLATFORM_CLUSTER_COUNT)
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return PSCI_E_NOT_PRESENT;
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/*
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* Validate cpu_id by checking whether it represents a CPU in
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* one of the two clusters present on the platform.
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*/
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if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
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return PSCI_E_NOT_PRESENT;
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if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) ||
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(cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) {
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ret = PSCI_E_NOT_PRESENT;
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} else {
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/* calculate the core position */
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pos = cpu_id + (cluster_id << 2U);
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/* calculate the core position */
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pos = cpu_id + (cluster_id << 2);
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/* check for non-existent CPUs */
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if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) {
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ret = PSCI_E_NOT_PRESENT;
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} else {
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ret = (int32_t)pos;
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}
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}
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/* check for non-existent CPUs */
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if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3)
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return PSCI_E_NOT_PRESENT;
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return pos;
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return ret;
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}
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