Tegra: bpmp: return error if BPMP init fails
This patch returns error if BPMP initialization fails. The platform code marks the cluster as "runnning" since we wont be able to get it into the low power state without BPMP. Change-Id: I86f51d478626240bb7b4ccede8907674290c5dc1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
parent
601a8e5495
commit
d7be5e2e3a
|
@ -125,7 +125,7 @@ int tegra_bpmp_init(void)
|
||||||
val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
|
val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
|
||||||
if (val != SIGN_OF_LIFE) {
|
if (val != SIGN_OF_LIFE) {
|
||||||
ERROR("BPMP precessor not available\n");
|
ERROR("BPMP precessor not available\n");
|
||||||
ret = -ENOTSUP;
|
return -ENOTSUP;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* check if clock for the atomics block is enabled */
|
/* check if clock for the atomics block is enabled */
|
||||||
|
@ -158,7 +158,6 @@ int tegra_bpmp_init(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* mark state as "initialized" */
|
/* mark state as "initialized" */
|
||||||
if (ret == 0)
|
|
||||||
bpmp_init_state = BPMP_INIT_COMPLETE;
|
bpmp_init_state = BPMP_INIT_COMPLETE;
|
||||||
|
|
||||||
/* the channel values have to be visible across all cpus */
|
/* the channel values have to be visible across all cpus */
|
||||||
|
|
|
@ -104,7 +104,12 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
|
||||||
if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) {
|
if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) {
|
||||||
|
|
||||||
/* initialize the bpmp interface */
|
/* initialize the bpmp interface */
|
||||||
(void)tegra_bpmp_init();
|
ret = tegra_bpmp_init();
|
||||||
|
if (ret != 0U) {
|
||||||
|
|
||||||
|
/* Cluster idle not allowed */
|
||||||
|
target = PSCI_LOCAL_STATE_RUN;
|
||||||
|
} else {
|
||||||
|
|
||||||
/* Cluster idle */
|
/* Cluster idle */
|
||||||
data[0] = (uint32_t)cpu;
|
data[0] = (uint32_t)cpu;
|
||||||
|
@ -112,7 +117,8 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
|
||||||
data[2] = TEGRA_PM_SC1;
|
data[2] = TEGRA_PM_SC1;
|
||||||
ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE,
|
ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE,
|
||||||
(void *)&data, (int)sizeof(data),
|
(void *)&data, (int)sizeof(data),
|
||||||
(void *)&bpmp_reply, (int)sizeof(bpmp_reply));
|
(void *)&bpmp_reply,
|
||||||
|
(int)sizeof(bpmp_reply));
|
||||||
|
|
||||||
/* check if cluster idle entry is allowed */
|
/* check if cluster idle entry is allowed */
|
||||||
if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) {
|
if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) {
|
||||||
|
@ -120,11 +126,17 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
|
||||||
/* Cluster idle not allowed */
|
/* Cluster idle not allowed */
|
||||||
target = PSCI_LOCAL_STATE_RUN;
|
target = PSCI_LOCAL_STATE_RUN;
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
} else if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_POWERDN)) {
|
} else if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_POWERDN)) {
|
||||||
|
|
||||||
/* initialize the bpmp interface */
|
/* initialize the bpmp interface */
|
||||||
(void)tegra_bpmp_init();
|
ret = tegra_bpmp_init();
|
||||||
|
if (ret != 0U) {
|
||||||
|
|
||||||
|
/* Cluster power down not allowed */
|
||||||
|
target = PSCI_LOCAL_STATE_RUN;
|
||||||
|
} else {
|
||||||
|
|
||||||
/* Cluster power-down */
|
/* Cluster power-down */
|
||||||
data[0] = (uint32_t)cpu;
|
data[0] = (uint32_t)cpu;
|
||||||
|
@ -132,7 +144,8 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
|
||||||
data[2] = TEGRA_PM_SC1;
|
data[2] = TEGRA_PM_SC1;
|
||||||
ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE,
|
ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE,
|
||||||
(void *)&data, (int)sizeof(data),
|
(void *)&data, (int)sizeof(data),
|
||||||
(void *)&bpmp_reply, (int)sizeof(bpmp_reply));
|
(void *)&bpmp_reply,
|
||||||
|
(int)sizeof(bpmp_reply));
|
||||||
|
|
||||||
/* check if cluster power down is allowed */
|
/* check if cluster power down is allowed */
|
||||||
if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) {
|
if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) {
|
||||||
|
@ -140,6 +153,7 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
|
||||||
/* Cluster power down not allowed */
|
/* Cluster power down not allowed */
|
||||||
target = PSCI_LOCAL_STATE_RUN;
|
target = PSCI_LOCAL_STATE_RUN;
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
} else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) &&
|
} else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) &&
|
||||||
(target == PSTATE_ID_SOC_POWERDN)) {
|
(target == PSTATE_ID_SOC_POWERDN)) {
|
||||||
|
|
Loading…
Reference in New Issue