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css: Fix erroneous non-secure RAM base address/size for SGI-575 

SGI-575's NSRAM is neither in the same place nor the same size as Juno's.

Change-Id: Id6d692e9c7e9c1360014bb525eda966ebe29c823
Signed-off-by: Chris Kay <chris.kay@arm.com>
This commit is contained in:
Chris Kay 2018-05-10 14:27:45 +01:00
parent 885ca54a75
commit d7ecac73b5
3 changed files with 6 additions and 3 deletions
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3
include/plat/arm/css/common/css_def.h
View File

@ -22,9 +22,6 @@
#define CSS_DEVICE_BASE 0x20000000
#define CSS_DEVICE_SIZE 0x0e000000
#define NSRAM_BASE 0x2e000000
#define NSRAM_SIZE 0x00008000
/* System Security Control Registers */
#define SSC_REG_BASE 0x2a420000
#define SSC_GPRETN (SSC_REG_BASE + 0x030)

3
plat/arm/board/juno/include/platform_def.h
View File

@ -56,6 +56,9 @@
/* Use the bypass address */
#define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
#define NSRAM_BASE 0x2e000000
#define NSRAM_SIZE 0x00008000 /* 32KB */
/* virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000

3
plat/arm/css/sgi/include/platform_def.h
View File

@ -52,6 +52,9 @@
#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */
#define PLAT_ARM_NSRAM_BASE 0x06000000
#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
#define PLAT_MAX_PWR_LVL 1
#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \