aarch64: Enable Statistical Profiling Extensions for lower ELs
SPE is only supported in non-secure state. Accesses to SPE specific registers from SEL1 will trap to EL3. During a world switch, before `TTBR` is modified the SPE profiling buffers are drained. This is to avoid a potential invalid memory access in SEL1. SPE is architecturally specified only for AArch64. Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
This commit is contained in:
dp-arm
Dimitris Papastamos
parent
18f2efd67d
commit
d832aee900
2
Makefile
2
Makefile
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@ -454,6 +454,7 @@ $(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
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$(eval $(call assert_boolean,USE_COHERENT_MEM))
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$(eval $(call assert_boolean,USE_TBBR_DEFS))
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$(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY))
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$(eval $(call assert_boolean,ENABLE_SPE_FOR_LOWER_ELS))
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$(eval $(call assert_numeric,ARM_ARCH_MAJOR))
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$(eval $(call assert_numeric,ARM_ARCH_MINOR))
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@ -493,6 +494,7 @@ $(eval $(call add_define,TRUSTED_BOARD_BOOT))
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$(eval $(call add_define,USE_COHERENT_MEM))
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$(eval $(call add_define,USE_TBBR_DEFS))
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$(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY))
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$(eval $(call add_define,ENABLE_SPE_FOR_LOWER_ELS))
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# Define the EL3_PAYLOAD_BASE flag only if it is provided.
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ifdef EL3_PAYLOAD_BASE
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@ -542,6 +542,11 @@ performed.
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cluster platforms). If this option is enabled, then warm boot path
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enables D-caches immediately after enabling MMU. This option defaults to 0.
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* `ENABLE_SPE_FOR_LOWER_ELS` : Boolean option to enable Statistical Profiling
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extensions. This is an optional architectural feature available only for
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AArch64 8.2 onwards. This option defaults to 1 but is automatically
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disabled when the target architecture is AArch32 or AArch64 8.0/8.1.
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#### ARM development platform specific build options
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* `ARM_BL31_IN_DRAM`: Boolean option to select loading of BL31 in TZC secured
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@ -95,6 +95,10 @@
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* MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
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* privileged debug from S-EL1.
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*
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* MDCR_EL3.NSPB (ARM v8.2): SPE enabled in non-secure state and
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* disabled in secure state. Accesses to SPE registers at SEL1 generate
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* trap exceptions to EL3.
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*
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* MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
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* access to the powerdown debug registers do not trap to EL3.
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*
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@ -108,6 +112,19 @@
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*/
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mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) \
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& ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT | MDCR_TPM_BIT))
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#if ENABLE_SPE_FOR_LOWER_ELS
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/* Detect if SPE is implemented */
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mrs x1, id_aa64dfr0_el1
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ubfx x1, x1, #ID_AA64DFR0_PMS_SHIFT, #ID_AA64DFR0_PMS_LENGTH
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cmp x1, #0x1
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b.ne 1f
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/* Enable SPE for use by normal world */
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orr x0, x0, #MDCR_NSPB(MDCR_NSPB_EL1)
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1:
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#endif
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msr mdcr_el3, x0
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/* ---------------------------------------------------------------------
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@ -110,6 +110,11 @@
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#define ID_AA64PFR0_EL3_SHIFT U(12)
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#define ID_AA64PFR0_ELX_MASK U(0xf)
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/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
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#define ID_AA64DFR0_PMS_SHIFT U(32)
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#define ID_AA64DFR0_PMS_LENGTH U(4)
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#define ID_AA64DFR0_PMS_MASK U(0xf)
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#define EL_IMPL_NONE U(0)
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#define EL_IMPL_A64ONLY U(1)
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#define EL_IMPL_A64_A32 U(2)
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@ -189,6 +194,8 @@
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#define MDCR_SPD32_DISABLE U(0x2)
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#define MDCR_SPD32_ENABLE U(0x3)
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#define MDCR_SDD_BIT (U(1) << 16)
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#define MDCR_NSPB(x) ((x) << 12)
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#define MDCR_NSPB_EL1 U(0x3)
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#define MDCR_TDOSA_BIT (U(1) << 10)
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#define MDCR_TDA_BIT (U(1) << 9)
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#define MDCR_TPM_BIT (U(1) << 6)
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@ -199,6 +206,9 @@
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#endif
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/* MDCR_EL2 definitions */
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#define MDCR_EL2_TPMS (U(1) << 14)
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#define MDCR_EL2_E2PB(x) ((x) << 12)
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#define MDCR_EL2_E2PB_EL1 U(0x3)
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#define MDCR_EL2_TDRA_BIT (U(1) << 11)
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#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
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#define MDCR_EL2_TDA_BIT (U(1) << 9)
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@ -184,6 +184,7 @@ DEFINE_SYSREG_WRITE_CONST_FUNC(daifclr)
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DEFINE_SYSREG_READ_FUNC(par_el1)
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DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
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DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
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DEFINE_SYSREG_READ_FUNC(CurrentEl)
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DEFINE_SYSREG_RW_FUNCS(daif)
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DEFINE_SYSREG_RW_FUNCS(spsr_el1)
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@ -308,6 +308,7 @@ CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx),
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* Function prototypes
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******************************************************************************/
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void el1_sysregs_context_save(el1_sys_regs_t *regs);
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void el1_sysregs_context_save_post_ops(void);
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void el1_sysregs_context_restore(el1_sys_regs_t *regs);
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#if CTX_INCLUDE_FPREGS
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void fpregs_context_save(fp_regs_t *regs);
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@ -218,4 +218,7 @@ int arm_execution_state_switch(unsigned int smc_fid,
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uint32_t cookie_lo,
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void *handle);
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/* Disable Statistical Profiling Extensions helper */
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void arm_disable_spe(void);
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#endif /* __PLAT_ARM_H__ */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,6 +9,7 @@
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#include <context.h>
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.global el1_sysregs_context_save
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.global el1_sysregs_context_save_post_ops
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.global el1_sysregs_context_restore
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#if CTX_INCLUDE_FPREGS
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.global fpregs_context_save
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@ -108,6 +109,36 @@ func el1_sysregs_context_save
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ret
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endfunc el1_sysregs_context_save
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/* -----------------------------------------------------
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* The following function strictly follows the AArch64
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* PCS to use x9-x17 (temporary caller-saved registers)
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* to do post operations after saving the EL1 system
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* register context.
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* -----------------------------------------------------
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*/
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func el1_sysregs_context_save_post_ops
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#if ENABLE_SPE_FOR_LOWER_ELS
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/* Detect if SPE is implemented */
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mrs x9, id_aa64dfr0_el1
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ubfx x9, x9, #ID_AA64DFR0_PMS_SHIFT, #ID_AA64DFR0_PMS_LENGTH
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cmp x9, #0x1
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b.ne 1f
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/*
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* Before switching from normal world to secure world
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* the profiling buffers need to be drained out to memory. This is
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* required to avoid an invalid memory access when TTBR is switched
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* for entry to SEL1.
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*/
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.arch armv8.2-a+profile
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psb csync
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dsb nsh
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.arch armv8-a
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1:
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#endif
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ret
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endfunc el1_sysregs_context_save_post_ops
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/* -----------------------------------------------------
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* The following function strictly follows the AArch64
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* PCS to use x9-x17 (temporary caller-saved registers)
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@ -343,7 +374,7 @@ func restore_gp_registers_callee_eret
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ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
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ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
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ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
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ldp x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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ldp x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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msr sp_el0, x17
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ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
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eret
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@ -218,7 +218,7 @@ void cm_init_my_context(const entry_point_info_t *ep)
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******************************************************************************/
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void cm_prepare_el3_exit(uint32_t security_state)
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{
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uint32_t sctlr_elx, scr_el3;
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uint32_t sctlr_elx, scr_el3, mdcr_el2;
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cpu_context_t *ctx = cm_get_context(security_state);
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assert(ctx);
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@ -315,6 +315,13 @@ void cm_prepare_el3_exit(uint32_t security_state)
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* relying on hw. Some fields are architecturally
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* UNKNOWN on reset.
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*
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* MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
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* profiling controls to EL2.
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*
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* MDCR_EL2.E2PB (ARM v8.2): SPE enabled in non-secure
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* state. Accesses to profiling buffer controls at
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* non-secure EL1 are not trapped to EL2.
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*
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* MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
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* EL1 System register accesses to the Debug ROM
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* registers are not trapped to EL2.
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@ -343,13 +350,32 @@ void cm_prepare_el3_exit(uint32_t security_state)
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* MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
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* architecturally-defined reset value.
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*/
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write_mdcr_el2((MDCR_EL2_RESET_VAL |
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mdcr_el2 = ((MDCR_EL2_RESET_VAL |
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((read_pmcr_el0() & PMCR_EL0_N_BITS)
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>> PMCR_EL0_N_SHIFT)) &
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~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT
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| MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT
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| MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT
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| MDCR_EL2_TPMCR_BIT));
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#if ENABLE_SPE_FOR_LOWER_ELS
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uint64_t id_aa64dfr0_el1;
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/* Detect if SPE is implemented */
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id_aa64dfr0_el1 = read_id_aa64dfr0_el1() >>
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ID_AA64DFR0_PMS_SHIFT;
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if ((id_aa64dfr0_el1 & ID_AA64DFR0_PMS_MASK) == 1) {
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/*
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* Make sure traps to EL2 are not generated if
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* EL2 is implemented but not used.
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*/
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mdcr_el2 &= ~MDCR_EL2_TPMS;
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mdcr_el2 |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
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}
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#endif
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write_mdcr_el2(mdcr_el2);
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/*
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* Initialise HSTR_EL2. All fields are architecturally
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* UNKNOWN on reset.
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@ -389,6 +415,7 @@ void cm_el1_sysregs_context_save(uint32_t security_state)
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assert(ctx);
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el1_sysregs_context_save(get_sysregs_ctx(ctx));
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el1_sysregs_context_save_post_ops();
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}
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void cm_el1_sysregs_context_restore(uint32_t security_state)
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@ -136,3 +136,20 @@ V := 0
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# required to enable cache coherency after warm reset (eg: single cluster
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# platforms).
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WARMBOOT_ENABLE_DCACHE_EARLY := 0
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# By default, enable Statistical Profiling Extensions.
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# The top level Makefile will disable this feature depending on
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# the target architecture and version number.
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ENABLE_SPE_FOR_LOWER_ELS := 1
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# SPE is enabled by default but only supported on AArch64 8.2 onwards.
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# Disable it in all other cases.
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ifeq (${ARCH},aarch32)
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override ENABLE_SPE_FOR_LOWER_ELS := 0
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else
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ifeq (${ARM_ARCH_MAJOR},8)
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ifeq ($(ARM_ARCH_MINOR),$(filter $(ARM_ARCH_MINOR),0 1))
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ENABLE_SPE_FOR_LOWER_ELS := 0
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endif
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endif
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endif
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@ -48,6 +48,14 @@ static void fvp_cluster_pwrdwn_common(void)
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{
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uint64_t mpidr = read_mpidr_el1();
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#if ENABLE_SPE_FOR_LOWER_ELS
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/*
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* On power down we need to disable statistical profiling extensions
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* before exiting coherency.
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*/
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arm_disable_spe();
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#endif
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/* Disable coherency if this cluster is to be turned off */
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fvp_interconnect_disable();
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@ -12,6 +12,7 @@
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl arm_disable_spe
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/* -----------------------------------------------------
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@ -86,3 +87,31 @@ endfunc plat_crash_console_flush
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func platform_mem_init
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ret
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endfunc platform_mem_init
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/* -----------------------------------------------------
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* void arm_disable_spe (void);
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* -----------------------------------------------------
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*/
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#if ENABLE_SPE_FOR_LOWER_ELS
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func arm_disable_spe
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/* Detect if SPE is implemented */
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mrs x0, id_aa64dfr0_el1
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ubfx x0, x0, #ID_AA64DFR0_PMS_SHIFT, #ID_AA64DFR0_PMS_LENGTH
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cmp x0, #0x1
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b.ne 1f
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/* Drain buffered data */
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.arch armv8.2-a+profile
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psb csync
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dsb nsh
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/* Disable Profiling Buffer */
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mrs x0, pmblimitr_el1
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bic x0, x0, #1
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msr pmblimitr_el1, x0
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isb
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.arch armv8-a
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1:
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ret
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endfunc arm_disable_spe
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#endif
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