xlat lib v2: Refactor the functions enabling the MMU
This patch refactors both the AArch32 and AArch64 versions of the function enable_mmu_arch(). In both versions, the code now computes the VMSA-related system registers upfront then program them in one go (rather than interleaving the 2). In the AArch64 version, this allows to reduce the amount of code generated by the C preprocessor and limits it to the actual differences between EL1 and EL3. In the AArch32 version, this patch also removes the function enable_mmu_internal_secure() and moves its code directly inside enable_mmu_arch(), as it was its only caller. Change-Id: I35c09b6db4404916cbb2e2fd3fda2ad59f935954 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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@ -82,16 +82,20 @@ uint64_t xlat_arch_get_xn_desc(int el __unused)
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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* Function for enabling the MMU in Secure PL1, assuming that the
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* Function for enabling the MMU in Secure PL1, assuming that the page tables
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* page-tables have already been created.
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* have already been created.
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******************************************************************************/
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******************************************************************************/
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void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table)
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void enable_mmu_arch(unsigned int flags,
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uint64_t *base_table,
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unsigned long long max_pa)
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{
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{
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u_register_t mair0, ttbcr, sctlr;
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u_register_t mair0, ttbcr, sctlr;
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uint64_t ttbr0;
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uint64_t ttbr0;
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assert(IS_IN_SECURE());
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assert(IS_IN_SECURE());
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assert((read_sctlr() & SCTLR_M_BIT) == 0);
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sctlr = read_sctlr();
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assert((sctlr & SCTLR_M_BIT) == 0);
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/* Invalidate TLBs at the current exception level */
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/* Invalidate TLBs at the current exception level */
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tlbiall();
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tlbiall();
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@ -102,29 +106,47 @@ void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table)
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ATTR_IWBWA_OWBWA_NTR_INDEX);
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ATTR_IWBWA_OWBWA_NTR_INDEX);
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mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
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mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE,
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ATTR_NON_CACHEABLE_INDEX);
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ATTR_NON_CACHEABLE_INDEX);
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write_mair0(mair0);
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/*
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/*
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* Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1.
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* Configure the control register for stage 1 of the PL1&0 translation
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* regime.
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*/
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/* Use the Long-descriptor translation table format. */
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ttbcr = TTBCR_EAE_BIT;
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/*
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* Disable translation table walk for addresses that are translated
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* using TTBR1. Therefore, only TTBR0 is used.
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*/
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ttbcr |= TTBCR_EPD1_BIT;
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/*
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* Limit the input address ranges and memory region sizes translated
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* using TTBR0 to the given virtual address space size.
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*/
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ttbcr |= 32 - __builtin_ctzl((uintptr_t) PLAT_VIRT_ADDR_SPACE_SIZE);
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/*
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* Set the cacheability and shareability attributes for memory
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* associated with translation table walks using TTBR0.
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*/
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*/
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if (flags & XLAT_TABLE_NC) {
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if (flags & XLAT_TABLE_NC) {
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/* Inner & outer non-cacheable non-shareable. */
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/* Inner & outer non-cacheable non-shareable. */
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ttbcr = TTBCR_EAE_BIT |
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ttbcr |= TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
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TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
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TTBCR_RGN0_INNER_NC;
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TTBCR_RGN0_INNER_NC |
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(32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
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} else {
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} else {
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/* Inner & outer WBWA & shareable. */
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/* Inner & outer WBWA & shareable. */
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ttbcr = TTBCR_EAE_BIT |
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ttbcr |= TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
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TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
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TTBCR_RGN0_INNER_WBA;
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TTBCR_RGN0_INNER_WBA |
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(32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
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}
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}
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ttbcr |= TTBCR_EPD1_BIT;
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write_ttbcr(ttbcr);
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/* Set TTBR0 bits as well */
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/* Set TTBR0 bits as well */
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ttbr0 = (uint64_t)(uintptr_t) base_table;
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ttbr0 = (uint64_t)(uintptr_t) base_table;
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/* Now program the relevant system registers */
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write_mair0(mair0);
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write_ttbcr(ttbcr);
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write64_ttbr0(ttbr0);
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write64_ttbr0(ttbr0);
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write64_ttbr1(0);
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write64_ttbr1(0);
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@ -137,7 +159,6 @@ void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table)
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dsbish();
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dsbish();
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isb();
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isb();
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sctlr = read_sctlr();
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;
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if (flags & DISABLE_DCACHE)
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if (flags & DISABLE_DCACHE)
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@ -150,10 +171,3 @@ void enable_mmu_internal_secure(unsigned int flags, uint64_t *base_table)
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/* Ensure the MMU enable takes effect immediately */
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/* Ensure the MMU enable takes effect immediately */
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isb();
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isb();
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}
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}
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void enable_mmu_arch(unsigned int flags,
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uint64_t *base_table,
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unsigned long long max_pa)
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{
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enable_mmu_internal_secure(flags, base_table);
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}
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@ -22,8 +22,6 @@
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# define IMAGE_EL 1
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# define IMAGE_EL 1
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#endif
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#endif
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static unsigned long long tcr_ps_bits;
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static unsigned long long calc_physical_addr_size_bits(
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static unsigned long long calc_physical_addr_size_bits(
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unsigned long long max_addr)
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unsigned long long max_addr)
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{
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{
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@ -151,50 +149,23 @@ uint64_t xlat_arch_get_xn_desc(int el)
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* exception level, assuming that the pagetables have already been created.
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* exception level, assuming that the pagetables have already been created.
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*
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*
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* _el: Exception level at which the function will run
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* _el: Exception level at which the function will run
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* _tcr_extra: Extra bits to set in the TCR register. This mask will
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* be OR'ed with the default TCR value.
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* _tlbi_fct: Function to invalidate the TLBs at the current
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* _tlbi_fct: Function to invalidate the TLBs at the current
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* exception level
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* exception level
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******************************************************************************/
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******************************************************************************/
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#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
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#define DEFINE_ENABLE_MMU_EL(_el, _tlbi_fct) \
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void enable_mmu_internal_el##_el(unsigned int flags, \
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static void enable_mmu_internal_el##_el(int flags, \
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uint64_t *base_table) \
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uint64_t mair, \
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uint64_t tcr, \
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uint64_t ttbr) \
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{ \
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{ \
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uint64_t mair, tcr, ttbr; \
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uint32_t sctlr = read_sctlr_el##_el(); \
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uint32_t sctlr; \
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assert((sctlr & SCTLR_M_BIT) == 0); \
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\
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assert(IS_IN_EL(_el)); \
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assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
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\
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\
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/* Invalidate TLBs at the current exception level */ \
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/* Invalidate TLBs at the current exception level */ \
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_tlbi_fct(); \
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_tlbi_fct(); \
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\
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\
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/* Set attributes in the right indices of the MAIR */ \
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
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ATTR_IWBWA_OWBWA_NTR_INDEX); \
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mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \
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ATTR_NON_CACHEABLE_INDEX); \
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write_mair_el##_el(mair); \
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write_mair_el##_el(mair); \
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\
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/* Set TCR bits as well. */ \
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/* Set T0SZ to (64 - width of virtual address space) */ \
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if (flags & XLAT_TABLE_NC) { \
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/* Inner & outer non-cacheable non-shareable. */\
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tcr = TCR_SH_NON_SHAREABLE | \
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TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC | \
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(64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
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} else { \
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/* Inner & outer WBWA & shareable. */ \
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tcr = TCR_SH_INNER_SHAREABLE | \
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TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \
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(64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
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} \
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tcr |= _tcr_extra; \
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write_tcr_el##_el(tcr); \
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write_tcr_el##_el(tcr); \
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\
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/* Set TTBR bits as well */ \
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ttbr = (uint64_t) base_table; \
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write_ttbr0_el##_el(ttbr); \
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write_ttbr0_el##_el(ttbr); \
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\
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\
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/* Ensure all translation table writes have drained */ \
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/* Ensure all translation table writes have drained */ \
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@ -204,9 +175,7 @@ uint64_t xlat_arch_get_xn_desc(int el)
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dsbish(); \
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dsbish(); \
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isb(); \
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isb(); \
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\
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\
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sctlr = read_sctlr_el##_el(); \
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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\
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if (flags & DISABLE_DCACHE) \
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if (flags & DISABLE_DCACHE) \
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sctlr &= ~SCTLR_C_BIT; \
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sctlr &= ~SCTLR_C_BIT; \
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else \
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else \
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@ -220,30 +189,61 @@ uint64_t xlat_arch_get_xn_desc(int el)
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/* Define EL1 and EL3 variants of the function enabling the MMU */
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/* Define EL1 and EL3 variants of the function enabling the MMU */
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#if IMAGE_EL == 1
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#if IMAGE_EL == 1
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DEFINE_ENABLE_MMU_EL(1,
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DEFINE_ENABLE_MMU_EL(1, tlbivmalle1)
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(tcr_ps_bits << TCR_EL1_IPS_SHIFT),
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tlbivmalle1)
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#elif IMAGE_EL == 3
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#elif IMAGE_EL == 3
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DEFINE_ENABLE_MMU_EL(3,
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DEFINE_ENABLE_MMU_EL(3, tlbialle3)
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TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT),
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tlbialle3)
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#endif
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#endif
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void enable_mmu_arch(unsigned int flags,
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void enable_mmu_arch(unsigned int flags,
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uint64_t *base_table,
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uint64_t *base_table,
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unsigned long long max_pa)
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unsigned long long max_pa)
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{
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{
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uint64_t mair, ttbr, tcr;
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/* Set attributes in the right indices of the MAIR. */
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX);
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mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX);
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ttbr = (uint64_t) base_table;
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/*
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* Set TCR bits as well.
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*/
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/*
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* Limit the input address ranges and memory region sizes translated
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* using TTBR0 to the given virtual address space size.
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*/
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tcr = 64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE);
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/*
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* Set the cacheability and shareability attributes for memory
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* associated with translation table walks.
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*/
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if (flags & XLAT_TABLE_NC) {
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/* Inner & outer non-cacheable non-shareable. */
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tcr |= TCR_SH_NON_SHAREABLE |
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TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC;
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} else {
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/* Inner & outer WBWA & shareable. */
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tcr |= TCR_SH_INNER_SHAREABLE |
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TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA;
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}
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/*
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/*
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* It is safer to restrict the max physical address accessible by the
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* It is safer to restrict the max physical address accessible by the
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* hardware as much as possible.
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* hardware as much as possible.
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*/
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*/
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tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
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unsigned long long tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
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#if IMAGE_EL == 1
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#if IMAGE_EL == 1
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assert(IS_IN_EL(1));
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assert(IS_IN_EL(1));
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enable_mmu_internal_el1(flags, base_table);
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tcr |= tcr_ps_bits << TCR_EL1_IPS_SHIFT;
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enable_mmu_internal_el1(flags, mair, tcr, ttbr);
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#elif IMAGE_EL == 3
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#elif IMAGE_EL == 3
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assert(IS_IN_EL(3));
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assert(IS_IN_EL(3));
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enable_mmu_internal_el3(flags, base_table);
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tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT);
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enable_mmu_internal_el3(flags, mair, tcr, ttbr);
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#endif
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#endif
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}
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}
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