intel: Platform common code refactor
Pull out common code from agilex and stratix10 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
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@ -37,14 +37,14 @@ BL2_SOURCES += \
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lib/cpus/aarch64/cortex_a53.S \
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plat/intel/soc/agilex/bl2_plat_setup.c \
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plat/intel/soc/agilex/socfpga_storage.c \
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plat/intel/soc/agilex/bl2_plat_mem_params_desc.c \
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plat/intel/soc/common/bl2_plat_mem_params_desc.c \
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plat/intel/soc/agilex/soc/agilex_reset_manager.c \
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plat/intel/soc/agilex/soc/agilex_handoff.c \
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plat/intel/soc/agilex/soc/agilex_clock_manager.c \
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plat/intel/soc/agilex/soc/agilex_pinmux.c \
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plat/intel/soc/agilex/soc/agilex_memory_controller.c \
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plat/intel/soc/agilex/socfpga_delay_timer.c \
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plat/intel/soc/agilex/socfpga_image_load.c \
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plat/intel/soc/common/socfpga_delay_timer.c \
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plat/intel/soc/common/socfpga_image_load.c \
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plat/intel/soc/agilex/soc/agilex_system_manager.c \
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plat/intel/soc/agilex/soc/agilex_mailbox.c \
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plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
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@ -59,8 +59,8 @@ BL31_SOURCES += \
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plat/intel/soc/agilex/socfpga_sip_svc.c \
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plat/intel/soc/agilex/bl31_plat_setup.c \
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plat/intel/soc/agilex/socfpga_psci.c \
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plat/intel/soc/agilex/socfpga_topology.c \
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plat/intel/soc/agilex/socfpga_delay_timer.c \
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plat/intel/soc/common/socfpga_topology.c \
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plat/intel/soc/common/socfpga_delay_timer.c \
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plat/intel/soc/agilex/soc/agilex_reset_manager.c \
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plat/intel/soc/agilex/soc/agilex_pinmux.c \
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plat/intel/soc/agilex/soc/agilex_clock_manager.c \
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@ -9,8 +9,8 @@
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#define AGX_GLOBAL_TIMER 0xffd01000
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#define AGX_GLOBAL_TIMER_EN 0x3
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#define SOCFPGA_GLOBAL_TIMER 0xffd01000
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#define SOCFPGA_GLOBAL_TIMER_EN 0x3
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/********************************************************************
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* The timer delay function
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@ -35,5 +35,5 @@ static const timer_ops_t plat_timer_ops = {
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void socfpga_delay_timer_init(void)
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{
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timer_init(&plat_timer_ops);
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mmio_write_32(AGX_GLOBAL_TIMER, AGX_GLOBAL_TIMER_EN);
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mmio_write_32(SOCFPGA_GLOBAL_TIMER, SOCFPGA_GLOBAL_TIMER_EN);
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}
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@ -1,96 +0,0 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.h>
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#include <common/desc_image_load.h>
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#include <platform_def.h>
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#include <plat/common/platform.h>
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/*******************************************************************************
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* Following descriptor provides BL image/ep information that gets used
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* by BL2 to load the images and also subset of this information is
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* passed to next BL image. The image loading sequence is managed by
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* populating the images in required loading order. The image execution
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* sequence is managed by populating the `next_handoff_image_id` with
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* the next executable image id.
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******************************************************************************/
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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#ifdef SCP_BL2_BASE
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/* Fill SCP_BL2 related information if it exists */
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{
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.image_id = SCP_BL2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = SCP_BL2_BASE,
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.image_info.image_max_size = SCP_BL2_SIZE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#endif /* SCP_BL2_BASE */
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#ifdef EL3_PAYLOAD_BASE
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/* Fill EL3 payload related information (BL31 is EL3 payload)*/
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = EL3_PAYLOAD_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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#else /* EL3_PAYLOAD_BASE */
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/* Fill BL31 related information */
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL31_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = BL31_BASE,
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.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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#endif /* EL3_PAYLOAD_BASE */
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{
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.image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = PLAT_NS_IMAGE_OFFSET,
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.image_info.image_max_size =
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0x0 + 0x40000000 - PLAT_NS_IMAGE_OFFSET,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
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@ -1,39 +0,0 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#define S10_GLOBAL_TIMER 0xffd01000
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#define S10_GLOBAL_TIMER_EN 0x3
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/********************************************************************
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* The timer delay function
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********************************************************************/
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static uint32_t plat_get_timer_value(void)
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{
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/*
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* Generic delay timer implementation expects the timer to be a down
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* counter. We apply bitwise NOT operator to the tick values returned
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* by read_cntpct_el0() to simulate the down counter. The value is
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* clipped from 64 to 32 bits.
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*/
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return (uint32_t)(~read_cntpct_el0());
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}
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static const timer_ops_t plat_timer_ops = {
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.get_timer_value = plat_get_timer_value,
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.clk_mult = 1,
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.clk_div = PLAT_SYS_COUNTER_FREQ_IN_MHZ,
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};
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void plat_delay_timer_init(void)
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{
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timer_init(&plat_timer_ops);
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mmio_write_32(S10_GLOBAL_TIMER, S10_GLOBAL_TIMER_EN);
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}
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@ -1,50 +0,0 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <platform_def.h>
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#include <lib/psci/psci.h>
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static const unsigned char plat_power_domain_tree_desc[] = {1, 4};
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/*******************************************************************************
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* This function returns the default topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return plat_power_domain_tree_desc;
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}
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/*******************************************************************************
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* This function implements a part of the critical interface between the psci
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* generic layer and the platform that allows the former to query the platform
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* to convert an MPIDR to a unique linear index. An error code (-1) is returned
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* in case the MPIDR is invalid.
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******************************************************************************/
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int plat_core_pos_by_mpidr(u_register_t mpidr)
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{
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unsigned int cluster_id, cpu_id;
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mpidr &= MPIDR_AFFINITY_MASK;
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if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
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return -1;
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cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
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cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
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if (cluster_id >= PLATFORM_CLUSTER_COUNT)
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return -1;
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/*
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* Validate cpu_id by checking whether it represents a CPU in
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* one of the two clusters present on the platform.
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*/
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if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
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return -1;
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return (cpu_id + (cluster_id * 4));
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}
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@ -35,15 +35,15 @@ BL2_SOURCES += \
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drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
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plat/intel/soc/stratix10/bl2_plat_setup.c \
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plat/intel/soc/stratix10/plat_storage.c \
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plat/intel/soc/stratix10/bl2_plat_mem_params_desc.c \
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plat/intel/soc/common/bl2_plat_mem_params_desc.c \
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plat/intel/soc/stratix10/soc/s10_reset_manager.c \
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plat/intel/soc/stratix10/soc/s10_handoff.c \
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plat/intel/soc/stratix10/soc/s10_clock_manager.c \
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plat/intel/soc/stratix10/soc/s10_pinmux.c \
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plat/intel/soc/stratix10/soc/s10_memory_controller.c \
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plat/intel/soc/stratix10/plat_delay_timer.c \
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plat/intel/soc/common/socfpga_delay_timer.c \
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lib/cpus/aarch64/cortex_a53.S \
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plat/intel/soc/stratix10/stratix10_image_load.c \
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plat/intel/soc/common/socfpga_image_load.c \
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plat/intel/soc/stratix10/soc/s10_system_manager.c \
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common/desc_image_load.c \
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plat/intel/soc/stratix10/soc/s10_mailbox.c \
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@ -58,8 +58,8 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
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plat/intel/soc/stratix10/plat_sip_svc.c \
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plat/intel/soc/stratix10/bl31_plat_setup.c \
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plat/intel/soc/stratix10/plat_psci.c \
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plat/intel/soc/stratix10/plat_topology.c \
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plat/intel/soc/stratix10/plat_delay_timer.c \
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plat/intel/soc/common/socfpga_topology.c \
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plat/intel/soc/common/socfpga_delay_timer.c \
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plat/intel/soc/stratix10/soc/s10_reset_manager.c\
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plat/intel/soc/stratix10/soc/s10_pinmux.c \
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plat/intel/soc/stratix10/soc/s10_clock_manager.c\
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@ -1,32 +0,0 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/desc_image_load.h>
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/*******************************************************************************
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* This function flushes the data structures so that they are visible
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* in memory for the next BL image.
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******************************************************************************/
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void plat_flush_next_bl_params(void)
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{
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flush_bl_params_desc();
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}
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/*******************************************************************************
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* This function returns the list of loadable images.
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******************************************************************************/
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bl_load_info_t *plat_get_bl_image_load_info(void)
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{
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return get_bl_load_info_from_mem_params_desc();
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}
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/*******************************************************************************
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* This function returns the list of executable images.
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******************************************************************************/
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bl_params_t *plat_get_next_bl_params(void)
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{
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return get_next_bl_params_from_mem_params_desc();
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}
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