Merge "stm32mp1: allow non-secure access to clocks upon periph registration" into integration
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commit
d88e485ff8
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@ -233,10 +233,83 @@ void stm32mp_register_non_secure_periph(enum stm32mp_shres id)
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register_periph(id, SHRES_NON_SECURE);
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register_periph(id, SHRES_NON_SECURE);
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}
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}
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/* Currently allow full access by non-secure to platform clock services */
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static bool stm32mp_gpio_bank_is_secure(unsigned int bank)
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{
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unsigned int secure = 0U;
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unsigned int i;
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lock_registering();
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if (bank != GPIO_BANK_Z) {
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return false;
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}
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for (i = 0U; i < get_gpioz_nbpin(); i++) {
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if (periph_is_secure(STM32MP1_SHRES_GPIOZ(i))) {
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secure++;
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}
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}
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return secure == get_gpioz_nbpin();
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}
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bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
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bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
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{
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{
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enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT;
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switch (clock_id) {
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case CK_CSI:
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case CK_HSE:
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case CK_HSE_DIV2:
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case CK_HSI:
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case CK_LSE:
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case CK_LSI:
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case PLL1_P:
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case PLL1_Q:
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case PLL1_R:
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case PLL2_P:
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case PLL2_Q:
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case PLL2_R:
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case PLL3_P:
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case PLL3_Q:
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case PLL3_R:
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case RTCAPB:
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return true;
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return true;
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case GPIOZ:
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/* Allow clock access if at least one pin is non-secure */
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return !stm32mp_gpio_bank_is_secure(GPIO_BANK_Z);
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case CRYP1:
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shres_id = STM32MP1_SHRES_CRYP1;
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break;
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case HASH1:
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shres_id = STM32MP1_SHRES_HASH1;
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break;
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case I2C4_K:
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shres_id = STM32MP1_SHRES_I2C4;
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break;
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case I2C6_K:
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shres_id = STM32MP1_SHRES_I2C6;
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break;
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case IWDG1:
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shres_id = STM32MP1_SHRES_IWDG1;
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break;
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case RNG1_K:
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shres_id = STM32MP1_SHRES_RNG1;
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break;
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case RTC:
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shres_id = STM32MP1_SHRES_RTC;
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break;
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case SPI6_K:
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shres_id = STM32MP1_SHRES_SPI6;
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break;
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case USART1_K:
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shres_id = STM32MP1_SHRES_USART1;
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break;
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default:
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return false;
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}
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return periph_is_non_secure(shres_id);
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}
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}
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/* Currently allow full access by non-secure to platform reset services */
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/* Currently allow full access by non-secure to platform reset services */
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