intel: mailbox: Ensure time out duration is predictive

For each count down of time out counter, wait for number of
miliseconds to ensure the time out duration is predictive.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b
This commit is contained in:
Chee Hong Ang 2020-05-11 00:55:01 +08:00 committed by Abdul Halim, Muhammad Hadi Asyrafi
parent 6d9f9f5ea0
commit d96e7cda8a
5 changed files with 26 additions and 15 deletions

View File

@ -101,6 +101,8 @@ static const gicv2_driver_data_t plat_gicv2_gic_data = {
******************************************************************************/
void bl31_platform_setup(void)
{
socfpga_delay_timer_init();
/* Initialize the gic cpu and distributor interfaces */
gicv2_driver_init(&plat_gicv2_gic_data);
gicv2_distif_init();

View File

@ -25,7 +25,8 @@ PLAT_BL_COMMON_SOURCES := \
lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S
plat/intel/soc/common/aarch64/plat_helpers.S \
plat/intel/soc/common/socfpga_delay_timer.c
BL2_SOURCES += \
common/desc_image_load.c \
@ -44,7 +45,6 @@ BL2_SOURCES += \
plat/intel/soc/agilex/soc/agilex_mmc.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_emac.c \

View File

@ -89,7 +89,7 @@ int mailbox_read_response(uint32_t *job_id, uint32_t *response, int resp_len)
int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response,
int resp_len)
{
int timeout = 0xFFFFFF;
uint32_t timeout = 40U;
int rin = 0;
int rout = 0;
int resp_data = 0;
@ -97,13 +97,15 @@ int mailbox_poll_response(uint32_t job_id, int urgent, uint32_t *response,
while (1) {
while (timeout > 0 &&
!(mmio_read_32(MBOX_OFFSET +
MBOX_DOORBELL_FROM_SDM) & 1)) {
timeout--;
}
do {
if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)
& 1) {
break;
}
mdelay(25);
} while (--timeout != 0U);
if (!timeout) {
if (timeout == 0U) {
INFO("Timed out waiting for SDM\n");
return MBOX_TIMEOUT;
}
@ -164,7 +166,7 @@ int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len)
int rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
while (mbox_resp_len > 0) {
timeout = 0xFFFFFF;
timeout = 40;
mbox_resp_len--;
resp_data = mmio_read_32(MBOX_OFFSET +
MBOX_RESP_BUFFER +
@ -180,11 +182,16 @@ int iterate_resp(int mbox_resp_len, uint32_t *resp_buf, int resp_len)
mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
do {
timeout--;
rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
} while ((rout == rin) && (mbox_resp_len > 0) && (timeout > 0));
if (rout == rin) {
mdelay(25);
} else {
break;
}
timeout--;
} while ((mbox_resp_len > 0) && (timeout != 0U));
if (timeout == 0) {
if (timeout == 0U) {
INFO("Timed out waiting for SDM\n");
return MBOX_TIMEOUT;
}

View File

@ -109,6 +109,8 @@ static const gicv2_driver_data_t plat_gicv2_gic_data = {
******************************************************************************/
void bl31_platform_setup(void)
{
socfpga_delay_timer_init();
/* Initialize the gic cpu and distributor interfaces */
gicv2_driver_init(&plat_gicv2_gic_data);
gicv2_distif_init();

View File

@ -25,7 +25,8 @@ PLAT_BL_COMMON_SOURCES := \
lib/xlat_tables/aarch64/xlat_tables.c \
lib/xlat_tables/xlat_tables_common.c \
plat/intel/soc/common/aarch64/platform_common.c \
plat/intel/soc/common/aarch64/plat_helpers.S
plat/intel/soc/common/aarch64/plat_helpers.S \
plat/intel/soc/common/socfpga_delay_timer.c
BL2_SOURCES += \
common/desc_image_load.c \
@ -43,7 +44,6 @@ BL2_SOURCES += \
plat/intel/soc/stratix10/soc/s10_memory_controller.c \
plat/intel/soc/stratix10/soc/s10_pinmux.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/common/socfpga_storage.c \
plat/intel/soc/common/soc/socfpga_emac.c \