plat: marvell: add support for PLL 2.2GHz mode
Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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613bbde09e
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dc402531ef
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@ -96,6 +96,11 @@ void ap807_clocks_init(unsigned int freq_option)
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case CPU_2000_DDR_1200_RCLK_1200:
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case CPU_2000_DDR_1200_RCLK_1200:
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pll_set_freq(PLL_FREQ_2000);
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pll_set_freq(PLL_FREQ_2000);
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break;
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break;
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#ifdef MVEBU_SOC_AP807
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case CPU_2200_DDR_1200_RCLK_1200:
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pll_set_freq(PLL_FREQ_2200);
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break;
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#endif
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default:
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default:
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break;
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break;
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}
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}
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@ -21,11 +21,17 @@ enum hws_freq {
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DDR_FREQ_SAR
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DDR_FREQ_SAR
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};
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};
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#include <mvebu_def.h>
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enum cpu_clock_freq_mode {
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enum cpu_clock_freq_mode {
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CPU_2000_DDR_1200_RCLK_1200 = 0x0,
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CPU_2000_DDR_1200_RCLK_1200 = 0x0,
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CPU_2000_DDR_1050_RCLK_1050 = 0x1,
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CPU_2000_DDR_1050_RCLK_1050 = 0x1,
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CPU_1600_DDR_800_RCLK_800 = 0x4,
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CPU_1600_DDR_800_RCLK_800 = 0x4,
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#ifdef MVEBU_SOC_AP807
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CPU_2200_DDR_1200_RCLK_1200 = 0x6,
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#else
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CPU_1800_DDR_1200_RCLK_1200 = 0x6,
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CPU_1800_DDR_1200_RCLK_1200 = 0x6,
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#endif
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CPU_1800_DDR_1050_RCLK_1050 = 0x7,
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CPU_1800_DDR_1050_RCLK_1050 = 0x7,
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CPU_1600_DDR_900_RCLK_900 = 0x0B,
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CPU_1600_DDR_900_RCLK_900 = 0x0B,
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CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
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CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
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@ -89,6 +89,12 @@
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(0x1 << AVS_SOFT_RESET_OFFSET) | \
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(0x1 << AVS_SOFT_RESET_OFFSET) | \
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(0x1 << AVS_ENABLE_OFFSET))
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(0x1 << AVS_ENABLE_OFFSET))
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#define AVS_CN9130_HIGH_CLK_VALUE ((0x80 << 24) | \
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(0x2dc << 13) | \
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(0x2dc << 3) | \
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(0x1 << AVS_SOFT_RESET_OFFSET) | \
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(0x1 << AVS_ENABLE_OFFSET))
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#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8)
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#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8)
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#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6
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#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6
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#define EFUSE_SRV_CTRL_LD_SEL_USER_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS)
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#define EFUSE_SRV_CTRL_LD_SEL_USER_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS)
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@ -224,10 +230,19 @@ static void ble_plat_avs_config(void)
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/* Check which SoC is running and act accordingly */
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/* Check which SoC is running and act accordingly */
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if (ble_get_ap_type() == CHIP_ID_AP807) {
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if (ble_get_ap_type() == CHIP_ID_AP807) {
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/* Increase CPU voltage for higher CPU clock */
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/* Increase CPU voltage for higher CPU clock */
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if (freq_mode == CPU_2000_DDR_1200_RCLK_1200)
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switch (freq_mode) {
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case CPU_2000_DDR_1200_RCLK_1200:
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avs_val = AVS_A3900_HIGH_CLK_VALUE;
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avs_val = AVS_A3900_HIGH_CLK_VALUE;
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else
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break;
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#ifdef MVEBU_SOC_AP807
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case CPU_2200_DDR_1200_RCLK_1200:
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avs_val = AVS_CN9130_HIGH_CLK_VALUE;
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break;
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#endif
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default:
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avs_val = AVS_A3900_CLK_VALUE;
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avs_val = AVS_A3900_CLK_VALUE;
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}
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} else {
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} else {
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/* Check which SoC is running and act accordingly */
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/* Check which SoC is running and act accordingly */
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device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
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device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
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@ -463,7 +478,9 @@ static void ble_plat_svc_config(void)
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NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
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NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
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single_cluster == 0 ? "8040" : "8020", freq_pidi_mode);
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single_cluster == 0 ? "8040" : "8020", freq_pidi_mode);
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switch (freq_pidi_mode) {
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switch (freq_pidi_mode) {
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#ifndef MVEBU_SOC_AP807
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case CPU_1800_DDR_1200_RCLK_1200:
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case CPU_1800_DDR_1200_RCLK_1200:
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#endif
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case CPU_1800_DDR_1050_RCLK_1050:
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case CPU_1800_DDR_1050_RCLK_1050:
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if (perr[1])
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if (perr[1])
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goto perror;
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goto perror;
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