Merge "fdts: stm32mp1: realign device tree with kernel" into integration
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
dc57bea007
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@ -1,24 +1,23 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*
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* STM32MP157C DK1/DK2 BOARD configuration
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* 1x DDR3L 4Gb, 16-bit, 533MHz.
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* Reference used NT5CC256M16DP-DI from NANYA
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*
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* DDR type / Platform DDR3/3L
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* freq 533MHz
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* width 16
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* datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
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* DDR density 4
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* timing mode optimized
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* Scheduling/QoS options : type = 2
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* address mapping : RBC
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* Tc > + 85C : N
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*/
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#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.45"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x20000000
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/*
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* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
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* DDR type: DDR3 / DDR3L
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* DDR width: 16bits
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* DDR density: 4Gb
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* System frequency: 533000Khz
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* Relaxed Timing Mode: false
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* Address mapping type: RBC
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*
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* Save Date: 2020.02.20, save Time: 18:45:20
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*/
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#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x20000000
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#define DDR_MSTR 0x00041401
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#define DDR_MRCTRL0 0x00000010
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@ -50,15 +49,6 @@
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ADDRMAP1 0x00070707
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x1F000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x06060606
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#define DDR_ADDRMAP6 0x0F060606
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000C01
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@ -83,6 +73,15 @@
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#define DDR_PCFGQOS1_1 0x00800040
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#define DDR_PCFGWQOS0_1 0x01100C03
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#define DDR_PCFGWQOS1_1 0x01000200
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#define DDR_ADDRMAP1 0x00070707
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x1F000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x06060606
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#define DDR_ADDRMAP6 0x0F060606
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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@ -1,24 +1,23 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*
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* STM32MP157C ED1 BOARD configuration
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* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
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* Reference used NT5CC256M16DP-DI from NANYA
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*
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* DDR type / Platform DDR3/3L
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* freq 533MHz
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* width 32
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* datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
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* DDR density 8
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* timing mode optimized
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* Scheduling/QoS options : type = 2
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* address mapping : RBC
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* Tc > + 85C : N
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*/
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#define DDR_MEM_NAME "DDR3-1066/888 bin G 2x4Gb 533MHz v1.45"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x40000000
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/*
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* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
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* DDR type: DDR3 / DDR3L
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* DDR width: 32bits
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* DDR density: 8Gb
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* System frequency: 533000Khz
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* Relaxed Timing Mode: false
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* Address mapping type: RBC
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*
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* Save Date: 2020.02.20, save Time: 18:49:33
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*/
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#define DDR_MEM_NAME "DDR3-DDR3L 32bits 533000Khz"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x40000000
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#define DDR_MSTR 0x00040401
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#define DDR_MRCTRL0 0x00000010
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@ -50,15 +49,6 @@
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ADDRMAP1 0x00080808
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x00000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x07070707
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#define DDR_ADDRMAP6 0x0F070707
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000C01
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@ -83,6 +73,15 @@
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#define DDR_PCFGQOS1_1 0x00800040
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#define DDR_PCFGWQOS0_1 0x01100C03
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#define DDR_PCFGWQOS1_1 0x01000200
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#define DDR_ADDRMAP1 0x00080808
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x00000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x07070707
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#define DDR_ADDRMAP6 0x0F070707
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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@ -0,0 +1,292 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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&pinctrl {
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fmc_pins_a: fmc-0 {
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pins1 {
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pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
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<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
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<STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
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<STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
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<STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
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<STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
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<STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
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<STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
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<STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
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<STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
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<STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
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<STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
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<STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
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bias-disable;
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drive-push-pull;
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slew-rate = <1>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
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bias-pull-up;
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};
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};
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qspi_clk_pins_a: qspi-clk-0 {
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pins {
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pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
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bias-disable;
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drive-push-pull;
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slew-rate = <3>;
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};
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};
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qspi_bk1_pins_a: qspi-bk1-0 {
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pins1 {
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pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
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<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
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<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
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<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
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bias-disable;
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drive-push-pull;
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slew-rate = <1>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
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bias-pull-up;
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drive-push-pull;
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slew-rate = <1>;
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};
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};
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qspi_bk2_pins_a: qspi-bk2-0 {
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pins1 {
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pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
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<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
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<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
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<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
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bias-disable;
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drive-push-pull;
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slew-rate = <1>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
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bias-pull-up;
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drive-push-pull;
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slew-rate = <1>;
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};
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};
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rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 {
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pins {
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pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */
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};
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};
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sdmmc1_b4_pins_a: sdmmc1-b4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
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<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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slew-rate = <1>;
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drive-push-pull;
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bias-disable;
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};
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pins2 {
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pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
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slew-rate = <2>;
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drive-push-pull;
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bias-disable;
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};
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};
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sdmmc1_dir_pins_a: sdmmc1-dir-0 {
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pins1 {
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pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
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<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
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<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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};
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pins2{
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pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
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bias-pull-up;
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};
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};
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sdmmc2_b4_pins_a: sdmmc2-b4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
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<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
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<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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slew-rate = <1>;
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drive-push-pull;
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bias-pull-up;
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||||
};
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pins2 {
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pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
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slew-rate = <2>;
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drive-push-pull;
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bias-pull-up;
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};
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};
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sdmmc2_b4_pins_b: sdmmc2-b4-1 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
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<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
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<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
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||||
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
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||||
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
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||||
slew-rate = <1>;
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||||
drive-push-pull;
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bias-disable;
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||||
};
|
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pins2 {
|
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pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
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||||
slew-rate = <2>;
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||||
drive-push-pull;
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bias-disable;
|
||||
};
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||||
};
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||||
|
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sdmmc2_d47_pins_a: sdmmc2-d47-0 {
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pins {
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||||
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
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||||
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
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||||
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
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||||
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
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||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins_a: uart4-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins_b: uart4-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart7_pins_a: uart7-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
|
||||
<STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
|
||||
<STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart7_pins_b: uart7-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_pins_a: usart2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
|
||||
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
|
||||
<STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart3_pins_a: usart3-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
||||
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
||||
<STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart3_pins_b: usart3-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
||||
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
||||
<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_pins_a: usbotg_hs-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
|
||||
<STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
i2c4_pins_a: i2c4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
||||
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,612 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a7";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@a0021000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xa0021000 0x1000>,
|
||||
<0xa0022000 0x2000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
clk_csi: clk-csi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <4000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
timers12: timer@40006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40006000 0x400>;
|
||||
clocks = <&rcc TIM12_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@4000e000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x4000e000 0x400>;
|
||||
interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc USART2_K>;
|
||||
resets = <&rcc USART2_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@4000f000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x4000f000 0x400>;
|
||||
interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc USART3_K>;
|
||||
resets = <&rcc USART3_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@40010000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40010000 0x400>;
|
||||
interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc UART4_K>;
|
||||
resets = <&rcc UART4_R>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@40011000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc UART5_K>;
|
||||
resets = <&rcc UART5_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@40018000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40018000 0x400>;
|
||||
interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc UART7_K>;
|
||||
resets = <&rcc UART7_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@40019000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40019000 0x400>;
|
||||
interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc UART8_K>;
|
||||
resets = <&rcc UART8_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart6: serial@44003000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x44003000 0x400>;
|
||||
interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc USART6_K>;
|
||||
resets = <&rcc USART6_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timers15: timer@44006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x44006000 0x400>;
|
||||
clocks = <&rcc TIM15_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg_hs: usb-otg@49000000 {
|
||||
compatible = "st,stm32mp1-hsotg", "snps,dwc2";
|
||||
reg = <0x49000000 0x10000>;
|
||||
clocks = <&rcc USBO_K>;
|
||||
clock-names = "otg";
|
||||
resets = <&rcc USBO_R>;
|
||||
reset-names = "dwc2";
|
||||
interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
g-rx-fifo-size = <512>;
|
||||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
|
||||
dr_mode = "otg";
|
||||
usb33d-supply = <&usb33>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcc: rcc@50000000 {
|
||||
compatible = "st,stm32mp1-rcc", "syscon";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
secure-interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
||||
secure-interrupt-names = "wakeup";
|
||||
};
|
||||
|
||||
pwr_regulators: pwr@50001000 {
|
||||
compatible = "st,stm32mp1,pwr-reg";
|
||||
reg = <0x50001000 0x10>;
|
||||
st,tzcr = <&rcc 0x0 0x1>;
|
||||
|
||||
reg11: reg11 {
|
||||
regulator-name = "reg11";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
reg18: reg18 {
|
||||
regulator-name = "reg18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
usb33: usb33 {
|
||||
regulator-name = "usb33";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
pwr_mcu: pwr_mcu@50001014 {
|
||||
compatible = "st,stm32mp151-pwr-mcu", "syscon";
|
||||
reg = <0x50001014 0x4>;
|
||||
};
|
||||
|
||||
pwr_irq: pwr@50001020 {
|
||||
compatible = "st,stm32mp1-pwr";
|
||||
reg = <0x50001020 0x100>;
|
||||
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@5000d000 {
|
||||
compatible = "st,stm32mp1-exti", "syscon";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000d000 0x400>;
|
||||
|
||||
/* exti_pwr is an extra interrupt controller used for
|
||||
* EXTI 55 to 60. It's mapped on pwr interrupt
|
||||
* controller.
|
||||
*/
|
||||
exti_pwr: exti-pwr {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&pwr_irq>;
|
||||
st,irq-number = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
syscfg: syscon@50020000 {
|
||||
compatible = "st,stm32mp157-syscfg", "syscon";
|
||||
reg = <0x50020000 0x400>;
|
||||
clocks = <&rcc SYSCFG>;
|
||||
};
|
||||
|
||||
hash1: hash@54002000 {
|
||||
compatible = "st,stm32f756-hash";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc HASH1>;
|
||||
resets = <&rcc HASH1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rng1: rng@54003000 {
|
||||
compatible = "st,stm32-rng";
|
||||
reg = <0x54003000 0x400>;
|
||||
clocks = <&rcc RNG1_K>;
|
||||
resets = <&rcc RNG1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fmc: nand-controller@58002000 {
|
||||
compatible = "st,stm32mp15-fmc2";
|
||||
reg = <0x58002000 0x1000>,
|
||||
<0x80000000 0x1000>,
|
||||
<0x88010000 0x1000>,
|
||||
<0x88020000 0x1000>,
|
||||
<0x81000000 0x1000>,
|
||||
<0x89010000 0x1000>,
|
||||
<0x89020000 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc FMC_K>;
|
||||
resets = <&rcc FMC_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qspi: spi@58003000 {
|
||||
compatible = "st,stm32f469-qspi";
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
||||
reg-names = "qspi", "qspi_mm";
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc QSPI_K>;
|
||||
resets = <&rcc QSPI_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc1: sdmmc@58005000 {
|
||||
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00253180>;
|
||||
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cmd_irq";
|
||||
clocks = <&rcc SDMMC1_K>;
|
||||
clock-names = "apb_pclk";
|
||||
resets = <&rcc SDMMC1_R>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc2: sdmmc@58007000 {
|
||||
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00253180>;
|
||||
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
||||
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cmd_irq";
|
||||
clocks = <&rcc SDMMC2_K>;
|
||||
clock-names = "apb_pclk";
|
||||
resets = <&rcc SDMMC2_R>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iwdg2: watchdog@5a002000 {
|
||||
compatible = "st,stm32mp1-iwdg";
|
||||
reg = <0x5a002000 0x400>;
|
||||
secure-interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
||||
clock-names = "pclk", "lsi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphyc: usbphyc@5a006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32mp1-usbphyc";
|
||||
reg = <0x5a006000 0x1000>;
|
||||
clocks = <&rcc USBPHY_K>;
|
||||
resets = <&rcc USBPHY_R>;
|
||||
vdda1v1-supply = <®11>;
|
||||
vdda1v8-supply = <®18>;
|
||||
status = "disabled";
|
||||
|
||||
usbphyc_port0: usb-phy@0 {
|
||||
#phy-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
usbphyc_port1: usb-phy@1 {
|
||||
#phy-cells = <1>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
usart1: serial@5c000000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x5c000000 0x400>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc USART1_K>;
|
||||
resets = <&rcc USART1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi6: spi@5c001000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x5c001000 0x400>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc SPI6_K>;
|
||||
resets = <&rcc SPI6_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@5c002000 {
|
||||
compatible = "st,stm32mp15-i2c";
|
||||
reg = <0x5c002000 0x400>;
|
||||
interrupt-names = "event", "error";
|
||||
interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc I2C4_K>;
|
||||
resets = <&rcc I2C4_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
st,syscfg-fmp = <&syscfg 0x4 0x8>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iwdg1: watchdog@5c003000 {
|
||||
compatible = "st,stm32mp1-iwdg";
|
||||
reg = <0x5C003000 0x400>;
|
||||
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
|
||||
clock-names = "pclk", "lsi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@5c004000 {
|
||||
compatible = "st,stm32mp1-rtc";
|
||||
reg = <0x5c004000 0x400>;
|
||||
clocks = <&rcc RTCAPB>, <&rcc RTC>;
|
||||
clock-names = "pclk", "rtc_ck";
|
||||
interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsec: nvmem@5c005000 {
|
||||
compatible = "st,stm32mp15-bsec";
|
||||
reg = <0x5c005000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ts_cal1: calib@5c {
|
||||
reg = <0x5c 0x2>;
|
||||
};
|
||||
ts_cal2: calib@5e {
|
||||
reg = <0x5e 0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
etzpc: etzpc@5c007000 {
|
||||
compatible = "st,stm32-etzpc";
|
||||
reg = <0x5C007000 0x400>;
|
||||
clocks = <&rcc TZPC>;
|
||||
status = "disabled";
|
||||
secure-status = "okay";
|
||||
};
|
||||
|
||||
stgen: stgen@5c008000 {
|
||||
compatible = "st,stm32-stgen";
|
||||
reg = <0x5C008000 0x1000>;
|
||||
};
|
||||
|
||||
i2c6: i2c@5c009000 {
|
||||
compatible = "st,stm32mp15-i2c";
|
||||
reg = <0x5c009000 0x400>;
|
||||
interrupt-names = "event", "error";
|
||||
interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc I2C6_K>;
|
||||
resets = <&rcc I2C6_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
st,syscfg-fmp = <&syscfg 0x4 0x20>;
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tamp: tamp@5c00a000 {
|
||||
compatible = "st,stm32-tamp", "simple-bus", "syscon", "simple-mfd";
|
||||
reg = <0x5c00a000 0x400>;
|
||||
secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc RTCAPB>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Break node order to solve dependency probe issue between
|
||||
* pinctrl and exti.
|
||||
*/
|
||||
pinctrl: pin-controller@50002000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp157-pinctrl";
|
||||
ranges = <0 0x50002000 0xa400>;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&exti 0x60 0xff>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&rcc GPIOA>;
|
||||
st,bank-name = "GPIOA";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x400>;
|
||||
clocks = <&rcc GPIOB>;
|
||||
st,bank-name = "GPIOB";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x400>;
|
||||
clocks = <&rcc GPIOC>;
|
||||
st,bank-name = "GPIOC";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x400>;
|
||||
clocks = <&rcc GPIOD>;
|
||||
st,bank-name = "GPIOD";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x400>;
|
||||
clocks = <&rcc GPIOE>;
|
||||
st,bank-name = "GPIOE";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000 0x400>;
|
||||
clocks = <&rcc GPIOF>;
|
||||
st,bank-name = "GPIOF";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x6000 0x400>;
|
||||
clocks = <&rcc GPIOG>;
|
||||
st,bank-name = "GPIOG";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x7000 0x400>;
|
||||
clocks = <&rcc GPIOH>;
|
||||
st,bank-name = "GPIOH";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x8000 0x400>;
|
||||
clocks = <&rcc GPIOI>;
|
||||
st,bank-name = "GPIOI";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioj: gpio@5000b000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x9000 0x400>;
|
||||
clocks = <&rcc GPIOJ>;
|
||||
st,bank-name = "GPIOJ";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiok: gpio@5000c000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xa000 0x400>;
|
||||
clocks = <&rcc GPIOK>;
|
||||
st,bank-name = "GPIOK";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z@54004000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp157-z-pinctrl";
|
||||
ranges = <0 0x54004000 0x400>;
|
||||
pins-are-numbered;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&exti 0x60 0xff>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x400>;
|
||||
clocks = <&rcc GPIOZ>;
|
||||
st,bank-name = "GPIOZ";
|
||||
st,bank-ioport = <11>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp151.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a7";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
clocks = <&rcc CK_MPU>;
|
||||
clock-names = "cpu";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,373 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller@50002000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp157-pinctrl";
|
||||
ranges = <0 0x50002000 0xa400>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&rcc GPIOA>;
|
||||
st,bank-name = "GPIOA";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x400>;
|
||||
clocks = <&rcc GPIOB>;
|
||||
st,bank-name = "GPIOB";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x400>;
|
||||
clocks = <&rcc GPIOC>;
|
||||
st,bank-name = "GPIOC";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x3000 0x400>;
|
||||
clocks = <&rcc GPIOD>;
|
||||
st,bank-name = "GPIOD";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4000 0x400>;
|
||||
clocks = <&rcc GPIOE>;
|
||||
st,bank-name = "GPIOE";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000 0x400>;
|
||||
clocks = <&rcc GPIOF>;
|
||||
st,bank-name = "GPIOF";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x6000 0x400>;
|
||||
clocks = <&rcc GPIOG>;
|
||||
st,bank-name = "GPIOG";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x7000 0x400>;
|
||||
clocks = <&rcc GPIOH>;
|
||||
st,bank-name = "GPIOH";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x8000 0x400>;
|
||||
clocks = <&rcc GPIOI>;
|
||||
st,bank-name = "GPIOI";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioj: gpio@5000b000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x9000 0x400>;
|
||||
clocks = <&rcc GPIOJ>;
|
||||
st,bank-name = "GPIOJ";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiok: gpio@5000c000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xa000 0x400>;
|
||||
clocks = <&rcc GPIOK>;
|
||||
st,bank-name = "GPIOK";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fmc_pins_a: fmc-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
|
||||
<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
|
||||
<STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
|
||||
<STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
|
||||
<STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
|
||||
<STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
|
||||
<STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
|
||||
<STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
|
||||
<STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
|
||||
<STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
|
||||
<STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
|
||||
<STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
|
||||
<STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_bk1_pins_a: qspi-bk1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
|
||||
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
|
||||
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
|
||||
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_bk2_pins_a: qspi-bk2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
|
||||
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
|
||||
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
|
||||
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_clk_pins_a: qspi-clk-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
||||
slew-rate = <2>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
|
||||
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
|
||||
<STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins2{
|
||||
pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
||||
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
|
||||
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
|
||||
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
|
||||
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
|
||||
slew-rate = <2>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_d47_pins_a: sdmmc2-d47-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
|
||||
<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
|
||||
<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
|
||||
<STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins_a: uart4-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins_b: uart4-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart7_pins_a: uart7-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart3_pins_a: usart3-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
||||
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
||||
<STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart3_pins_b: usart3-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
||||
<STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
|
||||
<STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z@54004000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp157-z-pinctrl";
|
||||
ranges = <0 0x54004000 0x400>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x400>;
|
||||
clocks = <&rcc GPIOZ>;
|
||||
st,bank-name = "GPIOZ";
|
||||
st,bank-ioport = <11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4_pins_a: i2c4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
|
||||
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp153.dtsi"
|
||||
|
|
@ -9,21 +9,30 @@
|
|||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c.dtsi"
|
||||
#include "stm32mp157cac-pinctrl.dtsi"
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxac-pinctrl.dtsi"
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Arrow Electronics STM32MP157A Avenger96 board";
|
||||
compatible = "st,stm32mp157a-avenger96", "st,stm32mp157";
|
||||
compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc1;
|
||||
serial0 = &uart4;
|
||||
serial1 = &uart7;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
|
|
@ -43,16 +52,17 @@
|
|||
|
||||
st,main-control-register = <0x04>;
|
||||
st,vin-control-register = <0xc0>;
|
||||
st,usb-control-register = <0x20>;
|
||||
st,usb-control-register = <0x30>;
|
||||
|
||||
regulators {
|
||||
compatible = "st,stpmic1-regulators";
|
||||
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo2-supply = <&v3v3>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo5-supply = <&v3v3>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
pwr_sw1-supply = <&bst_out>;
|
||||
pwr_sw2-supply = <&bst_out>;
|
||||
|
||||
vddcore: buck1 {
|
||||
regulator-name = "vddcore";
|
||||
|
|
@ -135,6 +145,19 @@
|
|||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
bst_out: boost {
|
||||
regulator-name = "bst_out";
|
||||
};
|
||||
|
||||
vbus_otg: pwr_sw1 {
|
||||
regulator-name = "vbus_otg";
|
||||
};
|
||||
|
||||
vbus_sw: pwr_sw2 {
|
||||
regulator-name = "vbus_sw";
|
||||
regulator-active-discharge = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -142,56 +165,14 @@
|
|||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
&pwr_regulators {
|
||||
vdd-supply = <&vdd>;
|
||||
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
||||
broken-cd;
|
||||
st,sig-dir;
|
||||
st,neg-edge;
|
||||
st,use-ckin;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vdda>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ATF Specific */
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
||||
#include "stm32mp157c-security.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
gpio0 = &gpioa;
|
||||
gpio1 = &gpiob;
|
||||
gpio2 = &gpioc;
|
||||
gpio3 = &gpiod;
|
||||
gpio4 = &gpioe;
|
||||
gpio5 = &gpiof;
|
||||
gpio6 = &gpiog;
|
||||
gpio7 = &gpioh;
|
||||
gpio8 = &gpioi;
|
||||
gpio25 = &gpioz;
|
||||
i2c3 = &i2c4;
|
||||
};
|
||||
};
|
||||
|
||||
/* CLOCK init */
|
||||
&rcc {
|
||||
secure-status = "disabled";
|
||||
st,clksrc = <
|
||||
|
|
@ -260,24 +241,67 @@
|
|||
|
||||
/* VCO = 1300.0 MHz => P = 650 (CPU) */
|
||||
pll1: st,pll@0 {
|
||||
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
|
||||
frac = < 0x800 >;
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <0>;
|
||||
cfg = <2 80 0 0 0 PQR(1,0,0)>;
|
||||
frac = <0x800>;
|
||||
};
|
||||
|
||||
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
||||
pll2: st,pll@1 {
|
||||
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
||||
frac = < 0x1400 >;
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <1>;
|
||||
cfg = <2 65 1 0 0 PQR(1,1,1)>;
|
||||
frac = <0x1400>;
|
||||
};
|
||||
|
||||
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
||||
pll3: st,pll@2 {
|
||||
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
|
||||
frac = < 0x1a04 >;
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <2>;
|
||||
cfg = <1 33 1 16 36 PQR(1,1,1)>;
|
||||
frac = <0x1a04>;
|
||||
};
|
||||
|
||||
/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
|
||||
pll4: st,pll@3 {
|
||||
cfg = < 1 39 3 11 4 PQR(1,1,1) >;
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <3>;
|
||||
cfg = <1 39 3 11 4 PQR(1,1,1)>;
|
||||
};
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
||||
st,sig-dir;
|
||||
st,neg-edge;
|
||||
st,use-ckin;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vdd_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
/* On Low speed expansion header */
|
||||
label = "LS-UART1";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
/* On Low speed expansion header */
|
||||
label = "LS-UART0";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,13 +1,15 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2018-2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>.
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c.dtsi"
|
||||
#include "stm32mp157cac-pinctrl.dtsi"
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxac-pinctrl.dtsi"
|
||||
#include "stm32mp15xx-dkx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
|
||||
|
|
@ -22,290 +24,4 @@
|
|||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
st,digbypass;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
|
||||
pmic: stpmic@33 {
|
||||
compatible = "st,stpmic1";
|
||||
reg = <0x33>;
|
||||
interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "okay";
|
||||
|
||||
st,main-control-register = <0x04>;
|
||||
st,vin-control-register = <0xc0>;
|
||||
st,usb-control-register = <0x20>;
|
||||
|
||||
regulators {
|
||||
compatible = "st,stpmic1-regulators";
|
||||
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
|
||||
vddcore: buck1 {
|
||||
regulator-name = "vddcore";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_ddr: buck2 {
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd: buck3 {
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
st,mask-reset;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
v3v3: buck4 {
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <0>;
|
||||
};
|
||||
|
||||
v1v8_audio: ldo1 {
|
||||
regulator-name = "v1v8_audio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v3v3_hdmi: ldo2 {
|
||||
regulator-name = "v3v3_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vtt_ddr: ldo3 {
|
||||
regulator-name = "vtt_ddr";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_usb: ldo4 {
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdda: ldo5 {
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v1v2_hdmi: ldo6 {
|
||||
regulator-name = "v1v2_hdmi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_ddr: vref_ddr {
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwr {
|
||||
pwr-regulators {
|
||||
vdd-supply = <&vdd>;
|
||||
};
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7_pins_a>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usart3_pins_b>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* ATF Specific */
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
|
||||
#include "stm32mp157c-security.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
gpio0 = &gpioa;
|
||||
gpio1 = &gpiob;
|
||||
gpio2 = &gpioc;
|
||||
gpio3 = &gpiod;
|
||||
gpio4 = &gpioe;
|
||||
gpio5 = &gpiof;
|
||||
gpio6 = &gpiog;
|
||||
gpio7 = &gpioh;
|
||||
gpio8 = &gpioi;
|
||||
gpio25 = &gpioz;
|
||||
i2c3 = &i2c4;
|
||||
};
|
||||
};
|
||||
|
||||
/* CLOCK init */
|
||||
&rcc {
|
||||
secure-status = "disabled";
|
||||
st,clksrc = <
|
||||
CLK_MPU_PLL1P
|
||||
CLK_AXI_PLL2P
|
||||
CLK_MCU_PLL3P
|
||||
CLK_PLL12_HSE
|
||||
CLK_PLL3_HSE
|
||||
CLK_PLL4_HSE
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
|
||||
>;
|
||||
|
||||
st,clkdiv = <
|
||||
1 /*MPU*/
|
||||
0 /*AXI*/
|
||||
0 /*MCU*/
|
||||
1 /*APB1*/
|
||||
1 /*APB2*/
|
||||
1 /*APB3*/
|
||||
1 /*APB4*/
|
||||
2 /*APB5*/
|
||||
23 /*RTC*/
|
||||
0 /*MCO1*/
|
||||
0 /*MCO2*/
|
||||
>;
|
||||
|
||||
st,pkcs = <
|
||||
CLK_CKPER_HSE
|
||||
CLK_FMC_ACLK
|
||||
CLK_QSPI_ACLK
|
||||
CLK_ETH_DISABLED
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_DSI_DSIPLL
|
||||
CLK_STGEN_HSE
|
||||
CLK_USBPHY_HSE
|
||||
CLK_SPI2S1_PLL3Q
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL4P
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL4P
|
||||
CLK_FDCAN_PLL4R
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_LSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
/* VCO = 1300.0 MHz => P = 650 (CPU) */
|
||||
pll1: st,pll@0 {
|
||||
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
|
||||
frac = < 0x800 >;
|
||||
};
|
||||
|
||||
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
||||
pll2: st,pll@1 {
|
||||
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
||||
frac = < 0x1400 >;
|
||||
};
|
||||
|
||||
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
||||
pll3: st,pll@2 {
|
||||
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
|
||||
frac = < 0x1a04 >;
|
||||
};
|
||||
|
||||
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
|
||||
pll4: st,pll@3 {
|
||||
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
|
||||
};
|
||||
};
|
||||
|
||||
&bsec {
|
||||
board_id: board_id@ec {
|
||||
reg = <0xec 0x4>;
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,16 +1,33 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>.
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157a-dk1.dts"
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15xc.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxac-pinctrl.dtsi"
|
||||
#include "stm32mp15xx-dkx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
|
||||
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
serial1 = &usart3;
|
||||
serial2 = &uart7;
|
||||
serial3 = &usart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&cryp1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -5,8 +5,12 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c.dtsi"
|
||||
#include "stm32mp157caa-pinctrl.dtsi"
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15xc.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxaa-pinctrl.dtsi"
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C eval daughter";
|
||||
|
|
@ -16,20 +20,47 @@
|
|||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xC0000000 0x40000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
};
|
||||
};
|
||||
|
||||
&bsec {
|
||||
board_id: board_id@ec {
|
||||
reg = <0xec 0x4>;
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
st,digbypass;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vddcore>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vddcore>;
|
||||
};
|
||||
|
||||
&cryp1 {
|
||||
status="okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
pmic: stpmic@33 {
|
||||
|
|
@ -40,18 +71,15 @@
|
|||
#interrupt-cells = <2>;
|
||||
status = "okay";
|
||||
|
||||
st,main-control-register = <0x04>;
|
||||
st,vin-control-register = <0xc0>;
|
||||
st,usb-control-register = <0x20>;
|
||||
|
||||
regulators {
|
||||
compatible = "st,stpmic1-regulators";
|
||||
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo2-supply = <&v3v3>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo5-supply = <&v3v3>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
pwr_sw1-supply = <&bst_out>;
|
||||
pwr_sw2-supply = <&bst_out>;
|
||||
|
||||
vddcore: buck1 {
|
||||
regulator-name = "vddcore";
|
||||
|
|
@ -112,8 +140,6 @@
|
|||
|
||||
vdd_usb: ldo4 {
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_sd: ldo5 {
|
||||
|
|
@ -132,8 +158,31 @@
|
|||
vref_ddr: vref_ddr {
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
bst_out: boost {
|
||||
regulator-name = "bst_out";
|
||||
};
|
||||
|
||||
vbus_otg: pwr_sw1 {
|
||||
regulator-name = "vbus_otg";
|
||||
};
|
||||
|
||||
vbus_sw: pwr_sw2 {
|
||||
regulator-name = "vbus_sw";
|
||||
regulator-active-discharge = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
onkey {
|
||||
compatible = "st,stpmic1-onkey";
|
||||
power-off-time-sec = <10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "st,stpmic1-wdt";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -143,81 +192,11 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pwr {
|
||||
pwr-regulators {
|
||||
vdd-supply = <&vdd>;
|
||||
};
|
||||
&pwr_regulators {
|
||||
vdd-supply = <&vdd>;
|
||||
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
||||
broken-cd;
|
||||
st,sig-dir;
|
||||
st,neg-edge;
|
||||
st,use-ckin;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vdd_sd>;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-ddr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
st,neg-edge;
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
vqmmc-supply = <&v3v3>;
|
||||
mmc-ddr-3_3v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* ATF Specific */
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
||||
#include "stm32mp157c-security.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
gpio0 = &gpioa;
|
||||
gpio1 = &gpiob;
|
||||
gpio2 = &gpioc;
|
||||
gpio3 = &gpiod;
|
||||
gpio4 = &gpioe;
|
||||
gpio5 = &gpiof;
|
||||
gpio6 = &gpiog;
|
||||
gpio7 = &gpioh;
|
||||
gpio8 = &gpioi;
|
||||
gpio9 = &gpioj;
|
||||
gpio10 = &gpiok;
|
||||
gpio25 = &gpioz;
|
||||
i2c3 = &i2c4;
|
||||
};
|
||||
};
|
||||
|
||||
/* CLOCK init */
|
||||
&rcc {
|
||||
secure-status = "disabled";
|
||||
st,clksrc = <
|
||||
|
|
@ -308,10 +287,46 @@
|
|||
};
|
||||
};
|
||||
|
||||
&bsec {
|
||||
board_id: board_id@ec {
|
||||
reg = <0xec 0x4>;
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
};
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
||||
disable-wp;
|
||||
st,sig-dir;
|
||||
st,neg-edge;
|
||||
st,use-ckin;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vdd_sd>;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-ddr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
st,neg-edge;
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
vqmmc-supply = <&vdd>;
|
||||
mmc-ddr-3_3v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,41 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
stgen: stgen@5c008000 {
|
||||
compatible = "st,stm32-stgen";
|
||||
reg = <0x5C008000 0x1000>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&bsec {
|
||||
mac_addr: mac_addr@e4 {
|
||||
reg = <0xe4 0x6>;
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
};
|
||||
/* Spare field to align on 32-bit OTP granularity */
|
||||
spare_ns_ea: spare_ns_ea@ea {
|
||||
reg = <0xea 0x2>;
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&hash1 {
|
||||
secure-status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
compatible = "st,stm32-sdmmc2";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
compatible = "st,stm32-sdmmc2";
|
||||
};
|
||||
|
|
@ -1,374 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stm32mp1-clks.h>
|
||||
#include <dt-bindings/reset/stm32mp1-resets.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
intc: interrupt-controller@a0021000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xa0021000 0x1000>,
|
||||
<0xa0022000 0x2000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
clk_csi: clk-csi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <4000000>;
|
||||
};
|
||||
|
||||
clk_i2s_ckin: i2s_ckin {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
clk_dsi_phy: ck_dsi_phy {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
timers12: timer@40006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40006000 0x400>;
|
||||
clocks = <&rcc TIM12_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@4000e000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x4000e000 0x400>;
|
||||
clocks = <&rcc USART2_K>;
|
||||
resets = <&rcc USART2_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@4000f000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x4000f000 0x400>;
|
||||
clocks = <&rcc USART3_K>;
|
||||
resets = <&rcc USART3_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@40010000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc UART4_K>;
|
||||
resets = <&rcc UART4_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@40011000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
clocks = <&rcc UART5_K>;
|
||||
resets = <&rcc UART5_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
uart7: serial@40018000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40018000 0x400>;
|
||||
clocks = <&rcc UART7_K>;
|
||||
resets = <&rcc UART7_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@40019000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40019000 0x400>;
|
||||
clocks = <&rcc UART8_K>;
|
||||
resets = <&rcc UART8_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart6: serial@44003000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x44003000 0x400>;
|
||||
clocks = <&rcc USART6_K>;
|
||||
resets = <&rcc USART6_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timers15: timer@44006000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x44006000 0x400>;
|
||||
clocks = <&rcc TIM15_K>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc3: sdmmc@48004000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00253180>;
|
||||
reg = <0x48004000 0x400>, <0x48005000 0x400>;
|
||||
clocks = <&rcc SDMMC3_K>;
|
||||
clock-names = "apb_pclk";
|
||||
resets = <&rcc SDMMC3_R>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg_hs: usb-otg@49000000 {
|
||||
compatible = "st,stm32mp1-hsotg", "snps,dwc2";
|
||||
reg = <0x49000000 0x10000>;
|
||||
clocks = <&rcc USBO_K>;
|
||||
clock-names = "otg";
|
||||
resets = <&rcc USBO_R>;
|
||||
reset-names = "dwc2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcc: rcc@50000000 {
|
||||
compatible = "st,stm32mp1-rcc", "syscon";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pwr: pwr@50001000 {
|
||||
compatible = "st,stm32mp1-pwr", "syscon", "simple-mfd";
|
||||
reg = <0x50001000 0x400>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@5000d000 {
|
||||
compatible = "st,stm32mp1-exti", "syscon";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x5000d000 0x400>;
|
||||
|
||||
/* exti_pwr is an extra interrupt controller used for
|
||||
* EXTI 55 to 60. It's mapped on pwr interrupt
|
||||
* controller.
|
||||
*/
|
||||
exti_pwr: exti-pwr {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&pwr>;
|
||||
st,irq-number = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
syscfg: syscon@50020000 {
|
||||
compatible = "st,stm32mp157-syscfg", "syscon";
|
||||
reg = <0x50020000 0x400>;
|
||||
clocks = <&rcc SYSCFG>;
|
||||
};
|
||||
|
||||
cryp1: cryp@54001000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54001000 0x400>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hash1: hash@54002000 {
|
||||
compatible = "st,stm32f756-hash";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc HASH1>;
|
||||
resets = <&rcc HASH1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rng1: rng@54003000 {
|
||||
compatible = "st,stm32-rng";
|
||||
reg = <0x54003000 0x400>;
|
||||
clocks = <&rcc RNG1_K>;
|
||||
resets = <&rcc RNG1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fmc: nand-controller@58002000 {
|
||||
compatible = "st,stm32mp15-fmc2";
|
||||
reg = <0x58002000 0x1000>,
|
||||
<0x80000000 0x1000>,
|
||||
<0x88010000 0x1000>,
|
||||
<0x88020000 0x1000>,
|
||||
<0x81000000 0x1000>,
|
||||
<0x89010000 0x1000>,
|
||||
<0x89020000 0x1000>;
|
||||
clocks = <&rcc FMC_K>;
|
||||
resets = <&rcc FMC_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qspi: qspi@58003000 {
|
||||
compatible = "st,stm32f469-qspi";
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
|
||||
reg-names = "qspi", "qspi_mm";
|
||||
clocks = <&rcc QSPI_K>;
|
||||
resets = <&rcc QSPI_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc1: sdmmc@58005000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00253180>;
|
||||
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
|
||||
clocks = <&rcc SDMMC1_K>;
|
||||
clock-names = "apb_pclk";
|
||||
resets = <&rcc SDMMC1_R>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc2: sdmmc@58007000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00253180>;
|
||||
reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
|
||||
clocks = <&rcc SDMMC2_K>;
|
||||
clock-names = "apb_pclk";
|
||||
resets = <&rcc SDMMC2_R>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iwdg2: watchdog@5a002000 {
|
||||
compatible = "st,stm32mp1-iwdg";
|
||||
reg = <0x5a002000 0x400>;
|
||||
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
|
||||
clock-names = "pclk", "lsi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@5c000000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x5c000000 0x400>;
|
||||
interrupt-names = "event", "wakeup";
|
||||
interrupts-extended = <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&exti 26 1>;
|
||||
clocks = <&rcc USART1_K>;
|
||||
resets = <&rcc USART1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi6: spi@5c001000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x5c001000 0x400>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc SPI6_K>;
|
||||
resets = <&rcc SPI6_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@5c002000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x5c002000 0x400>;
|
||||
interrupt-names = "event", "error", "wakeup";
|
||||
interrupts-extended = <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&exti 24 1>;
|
||||
clocks = <&rcc I2C4_K>;
|
||||
resets = <&rcc I2C4_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@5c004000 {
|
||||
compatible = "st,stm32mp1-rtc";
|
||||
reg = <0x5c004000 0x400>;
|
||||
clocks = <&rcc RTCAPB>, <&rcc RTC>;
|
||||
clock-names = "pclk", "rtc_ck";
|
||||
interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&exti 19 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bsec: nvmem@5c005000 {
|
||||
compatible = "st,stm32mp15-bsec";
|
||||
reg = <0x5c005000 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ts_cal1: calib@5c {
|
||||
reg = <0x5c 0x2>;
|
||||
};
|
||||
ts_cal2: calib@5e {
|
||||
reg = <0x5e 0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
etzpc: etzpc@5c007000 {
|
||||
compatible = "st,stm32-etzpc";
|
||||
reg = <0x5C007000 0x400>;
|
||||
clocks = <&rcc TZPC>;
|
||||
status = "disabled";
|
||||
secure-status = "okay";
|
||||
};
|
||||
|
||||
i2c6: i2c@5c009000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x5c009000 0x400>;
|
||||
interrupt-names = "event", "error", "wakeup";
|
||||
interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&exti 54 1>;
|
||||
clocks = <&rcc I2C6_K>;
|
||||
resets = <&rcc I2C6_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,90 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
#include "stm32mp157-pinctrl.dtsi"
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller@50002000 {
|
||||
st,package = <STM32MP157CAA>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@5000b000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@5000c000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z@54004000 {
|
||||
st,package = <STM32MP157CAA>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,78 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
#include "stm32mp157-pinctrl.dtsi"
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller@50002000 {
|
||||
st,package = <STM32MP157CAC>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z@54004000 {
|
||||
st,package = <STM32MP157CAC>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp1: cryp@54001000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54001000 0x400>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,350 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
||||
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
|
||||
|
||||
/ {
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x20000000>;
|
||||
};
|
||||
|
||||
vin: vin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vin";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&bsec {
|
||||
board_id: board_id@ec {
|
||||
reg = <0xec 0x4>;
|
||||
st,non-secure-otp;
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
st,digbypass;
|
||||
};
|
||||
|
||||
&cpu0{
|
||||
cpu-supply = <&vddcore>;
|
||||
};
|
||||
|
||||
&cpu1{
|
||||
cpu-supply = <&vddcore>;
|
||||
};
|
||||
|
||||
&hash1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
pmic: stpmic@33 {
|
||||
compatible = "st,stpmic1";
|
||||
reg = <0x33>;
|
||||
interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "okay";
|
||||
|
||||
regulators {
|
||||
compatible = "st,stpmic1-regulators";
|
||||
buck1-supply = <&vin>;
|
||||
buck2-supply = <&vin>;
|
||||
buck3-supply = <&vin>;
|
||||
buck4-supply = <&vin>;
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo2-supply = <&vin>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo4-supply = <&vin>;
|
||||
ldo5-supply = <&vin>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
vref_ddr-supply = <&vin>;
|
||||
boost-supply = <&vin>;
|
||||
pwr_sw1-supply = <&bst_out>;
|
||||
pwr_sw2-supply = <&bst_out>;
|
||||
|
||||
vddcore: buck1 {
|
||||
regulator-name = "vddcore";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_ddr: buck2 {
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd: buck3 {
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
st,mask-reset;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
v3v3: buck4 {
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <0>;
|
||||
};
|
||||
|
||||
v1v8_audio: ldo1 {
|
||||
regulator-name = "v1v8_audio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v3v3_hdmi: ldo2 {
|
||||
regulator-name = "v3v3_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vtt_ddr: ldo3 {
|
||||
regulator-name = "vtt_ddr";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_usb: ldo4 {
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdda: ldo5 {
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v1v2_hdmi: ldo6 {
|
||||
regulator-name = "v1v2_hdmi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_ddr: vref_ddr {
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
bst_out: boost {
|
||||
regulator-name = "bst_out";
|
||||
};
|
||||
|
||||
vbus_otg: pwr_sw1 {
|
||||
regulator-name = "vbus_otg";
|
||||
};
|
||||
|
||||
vbus_sw: pwr_sw2 {
|
||||
regulator-name = "vbus_sw";
|
||||
regulator-active-discharge = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
};
|
||||
|
||||
&pwr_regulators {
|
||||
vdd-supply = <&vdd>;
|
||||
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&rcc {
|
||||
secure-status = "disabled";
|
||||
st,clksrc = <
|
||||
CLK_MPU_PLL1P
|
||||
CLK_AXI_PLL2P
|
||||
CLK_MCU_PLL3P
|
||||
CLK_PLL12_HSE
|
||||
CLK_PLL3_HSE
|
||||
CLK_PLL4_HSE
|
||||
CLK_RTC_LSE
|
||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
|
||||
>;
|
||||
|
||||
st,clkdiv = <
|
||||
1 /*MPU*/
|
||||
0 /*AXI*/
|
||||
0 /*MCU*/
|
||||
1 /*APB1*/
|
||||
1 /*APB2*/
|
||||
1 /*APB3*/
|
||||
1 /*APB4*/
|
||||
2 /*APB5*/
|
||||
23 /*RTC*/
|
||||
0 /*MCO1*/
|
||||
0 /*MCO2*/
|
||||
>;
|
||||
|
||||
st,pkcs = <
|
||||
CLK_CKPER_HSE
|
||||
CLK_FMC_ACLK
|
||||
CLK_QSPI_ACLK
|
||||
CLK_ETH_DISABLED
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_DSI_DSIPLL
|
||||
CLK_STGEN_HSE
|
||||
CLK_USBPHY_HSE
|
||||
CLK_SPI2S1_PLL3Q
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL4P
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL4P
|
||||
CLK_FDCAN_PLL4R
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_LSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
/* VCO = 1300.0 MHz => P = 650 (CPU) */
|
||||
pll1: st,pll@0 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <0>;
|
||||
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
|
||||
frac = < 0x800 >;
|
||||
};
|
||||
|
||||
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
||||
pll2: st,pll@1 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <1>;
|
||||
cfg = <2 65 1 0 0 PQR(1,1,1)>;
|
||||
frac = <0x1400>;
|
||||
};
|
||||
|
||||
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
||||
pll3: st,pll@2 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <2>;
|
||||
cfg = <1 33 1 16 36 PQR(1,1,1)>;
|
||||
frac = <0x1a04>;
|
||||
};
|
||||
|
||||
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
|
||||
pll4: st,pll@3 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <3>;
|
||||
cfg = <3 98 5 7 7 PQR(1,1,1)>;
|
||||
};
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
disable-wp;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timers15 {
|
||||
secure-status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7_pins_b>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usart3_pins_b>;
|
||||
uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
usb-role-switch;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
};
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AA>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@5000b000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@5000c000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
st,package = <STM32MP_PKG_AA>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AB>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <6>;
|
||||
gpio-ranges = <&pinctrl 6 86 6>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl 6 102 10>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <2>;
|
||||
gpio-ranges = <&pinctrl 0 112 2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AC>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
st,package = <STM32MP_PKG_AC>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AD>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <6>;
|
||||
gpio-ranges = <&pinctrl 6 86 6>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl 6 102 10>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <2>;
|
||||
gpio-ranges = <&pinctrl 0 112 2>;
|
||||
};
|
||||
};
|
||||
|
|
@ -26,6 +26,7 @@
|
|||
#define AF14 0xf
|
||||
#define AF15 0x10
|
||||
#define ANALOG 0x11
|
||||
#define RSVD 0x12
|
||||
|
||||
/* define Pins number*/
|
||||
#define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line))
|
||||
|
|
@ -33,9 +34,9 @@
|
|||
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
|
||||
|
||||
/* package information */
|
||||
#define STM32MP157CAA 0x1
|
||||
#define STM32MP157CAB 0x2
|
||||
#define STM32MP157CAC 0x4
|
||||
#define STM32MP157CAD 0x8
|
||||
#define STM32MP_PKG_AA 0x1
|
||||
#define STM32MP_PKG_AB 0x2
|
||||
#define STM32MP_PKG_AC 0x4
|
||||
#define STM32MP_PKG_AD 0x8
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
|
||||
|
|
|
|||
|
|
@ -513,7 +513,7 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
|
|||
******************************************************************************/
|
||||
#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
|
||||
#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
|
||||
#define DT_PWR_COMPAT "st,stm32mp1-pwr"
|
||||
#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
|
||||
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
|
||||
#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue