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arm-trusted-firmware
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Merge changes I0ae8a6ea,I0b4fc83e into integration 

* changes:
  feat(tc): Enable SVE for both secure and non-secure world
  feat(tc): populate HW_CONFIG in BL31
This commit is contained in:
Olivier Deprez 2021-09-07 18:00:44 +02:00 committed by TrustedFirmware Code Review
parent e843fb0a74 10198eab3a
commit dc8b361c78
6 changed files with 86 additions and 5 deletions
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4
plat/arm/board/tc/fdts/tc_fw_config.dts
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, Arm Limited. All rights reserved.
* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -26,7 +26,7 @@
hw-config {
load-address = <0x0 0x83000000>;
max-size = <0x01000000>;
max-size = <0x8000>;
id = <HW_CONFIG_ID>;
};
};

10
plat/arm/board/tc/include/platform_def.h
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@ -55,6 +55,14 @@
TC_TZC_DRAM1_BASE, \
TC_TZC_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
#define PLAT_HW_CONFIG_DTB_BASE ULL(0x83000000)
#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000)
#define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \
PLAT_HW_CONFIG_DTB_BASE, \
PLAT_HW_CONFIG_DTB_SIZE, \
MT_MEMORY | MT_RO | MT_NS)
/*
* Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to
* max size of BL32 image.
@ -122,7 +130,7 @@
* calculated using the current BL31 PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
#define PLAT_ARM_MAX_BL31_SIZE 0x3F000
/*
* Size of cacheable stacks

7
plat/arm/board/tc/platform.mk
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@ -31,6 +31,9 @@ GIC_ENABLE_V4_EXTN := 1
# GIC-600 configuration
GICV3_SUPPORT_GIC600 := 1
# Enable SVE
ENABLE_SVE_FOR_NS := 1
ENABLE_SVE_FOR_SWD := 1
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@ -77,6 +80,7 @@ BL1_SOURCES += ${INTERCONNECT_SOURCES} \
BL2_SOURCES += ${TC_BASE}/tc_security.c \
${TC_BASE}/tc_err.c \
${TC_BASE}/tc_trusted_boot.c \
${TC_BASE}/tc_bl2_setup.c \
lib/utils/mem_region.c \
drivers/arm/tzc/tzc400.c \
plat/arm/common/arm_tzc400.c \
@ -87,6 +91,9 @@ BL31_SOURCES += ${INTERCONNECT_SOURCES} \
${ENT_GIC_SOURCES} \
${TC_BASE}/tc_bl31_setup.c \
${TC_BASE}/tc_topology.c \
common/fdt_wrappers.c \
lib/fconf/fconf.c \
lib/fconf/fconf_dyn_cfg_getter.c \
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c

47
plat/arm/board/tc/tc_bl2_setup.c Normal file
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@ -0,0 +1,47 @@
/*
* Copyright (c) 2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <common/bl_common.h>
#include <common/desc_image_load.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <plat/arm/common/plat_arm.h>
/*******************************************************************************
* This function returns the list of executable images
******************************************************************************/
struct bl_params *plat_get_next_bl_params(void)
{
struct bl_params *arm_bl_params = arm_get_next_bl_params();
const struct dyn_cfg_dtb_info_t *fw_config_info;
bl_mem_params_node_t *param_node;
uintptr_t fw_config_base = 0U;
entry_point_info_t *ep_info;
/* Get BL31 image node */
param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
assert(param_node != NULL);
/* Get fw_config load address */
fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
assert(fw_config_info != NULL);
fw_config_base = fw_config_info->config_addr;
assert(fw_config_base != 0U);
/*
* Get the entry point info of BL31 image and override
* arg1 of entry point info with fw_config base address
*/
ep_info = &param_node->ep_info;
ep_info->args.arg1 = (uint32_t)fw_config_base;
return arm_bl_params;
}

20
plat/arm/board/tc/tc_bl31_setup.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,6 +13,8 @@
#include <common/debug.h>
#include <drivers/arm/css/css_mhu_doorbell.h>
#include <drivers/arm/css/scmi.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
@ -42,6 +44,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
/* Fill the properties struct with the info from the config dtb */
fconf_populate("FW_CONFIG", arg1);
}
void tc_bl31_common_platform_setup(void)
@ -53,3 +58,16 @@ const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
{
return css_scmi_override_pm_ops(ops);
}
void __init bl31_plat_arch_setup(void)
{
arm_bl31_plat_arch_setup();
/* HW_CONFIG was also loaded by BL2 */
const struct dyn_cfg_dtb_info_t *hw_config_info;
hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
assert(hw_config_info != NULL);
fconf_populate("HW_CONFIG", hw_config_info->config_addr);
}

3
plat/arm/board/tc/tc_plat.c
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -63,6 +63,7 @@ const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
TC_MAP_DEVICE,
PLAT_DTB_DRAM_NS,
#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif