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Merge pull request #1542 from antonio-nino-diaz-arm/an/bl31-misra 

Some MISRA fixes in BL31, cci and smmu
This commit is contained in:
Dimitris Papastamos 2018-08-30 16:18:49 +01:00 committed by GitHub
parent 7bb907e0d9 4213e9bacd
commit dcf95e7e90
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
17 changed files with 258 additions and 229 deletions
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11
bl31/bl31_main.c
View File

@ -103,9 +103,14 @@ void bl31_main(void)
/*
* If SPD had registerd an init hook, invoke it.
*/
if (bl32_init) {
if (bl32_init != NULL) {
INFO("BL31: Initializing BL32\n");
(*bl32_init)();
int32_t rc = (*bl32_init)();
if (rc != 0) {
ERROR("BL31: BL32 initialization failed (rc = %d)", rc);
}
}
/*
* We are ready to enter the next EL. Prepare entry into the image
@ -167,7 +172,7 @@ void bl31_prepare_next_image_entry(void)
/* Program EL3 registers to enable entry into the next EL */
next_image_info = bl31_plat_get_next_image_ep_info(image_type);
assert(next_image_info);
assert(next_image_info != NULL);
assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr));
INFO("BL31: Preparing for EL3 exit to %s world\n",

42
bl31/interrupt_mgmt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,7 +10,6 @@
#include <errno.h>
#include <interrupt_mgmt.h>
#include <platform.h>
#include <stdio.h>
/*******************************************************************************
* Local structure and corresponding array to keep track of the state of the
@ -47,8 +46,8 @@ static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES];
******************************************************************************/
static int32_t validate_interrupt_type(uint32_t type)
{
if (type == INTR_TYPE_S_EL1 || type == INTR_TYPE_NS ||
type == INTR_TYPE_EL3)
if ((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_NS) ||
(type == INTR_TYPE_EL3))
return 0;
return -EINVAL;
@ -59,17 +58,16 @@ static int32_t validate_interrupt_type(uint32_t type)
******************************************************************************/
static int32_t validate_routing_model(uint32_t type, uint32_t flags)
{
flags >>= INTR_RM_FLAGS_SHIFT;
flags &= INTR_RM_FLAGS_MASK;
uint32_t rm_flags = (flags >> INTR_RM_FLAGS_SHIFT) & INTR_RM_FLAGS_MASK;
if (type == INTR_TYPE_S_EL1)
return validate_sel1_interrupt_rm(flags);
return validate_sel1_interrupt_rm(rm_flags);
if (type == INTR_TYPE_NS)
return validate_ns_interrupt_rm(flags);
return validate_ns_interrupt_rm(rm_flags);
if (type == INTR_TYPE_EL3)
return validate_el3_interrupt_rm(flags);
return validate_el3_interrupt_rm(rm_flags);
return -EINVAL;
}
@ -106,10 +104,12 @@ static void set_scr_el3_from_rm(uint32_t type,
bit_pos = plat_interrupt_type_to_line(type, security_state);
intr_type_descs[type].scr_el3[security_state] = flag << bit_pos;
/* Update scr_el3 only if there is a context available. If not, it
/*
* Update scr_el3 only if there is a context available. If not, it
* will be updated later during context initialization which will obtain
* the scr_el3 value to be used via get_scr_el3_from_routing_model() */
if (cm_get_context(security_state))
* the scr_el3 value to be used via get_scr_el3_from_routing_model()
*/
if (cm_get_context(security_state) != NULL)
cm_write_scr_el3_bit(security_state, bit_pos, flag);
}
@ -124,11 +124,11 @@ int32_t set_routing_model(uint32_t type, uint32_t flags)
int32_t rc;
rc = validate_interrupt_type(type);
if (rc)
if (rc != 0)
return rc;
rc = validate_routing_model(type, flags);
if (rc)
if (rc != 0)
return rc;
/* Update the routing model in internal data structures */
@ -149,7 +149,7 @@ int disable_intr_rm_local(uint32_t type, uint32_t security_state)
{
uint32_t bit_pos, flag;
assert(intr_type_descs[type].handler);
assert(intr_type_descs[type].handler != NULL);
flag = get_interrupt_rm_flag(INTR_DEFAULT_RM, security_state);
@ -167,7 +167,7 @@ int enable_intr_rm_local(uint32_t type, uint32_t security_state)
{
uint32_t bit_pos, flag;
assert(intr_type_descs[type].handler);
assert(intr_type_descs[type].handler != NULL);
flag = get_interrupt_rm_flag(intr_type_descs[type].flags,
security_state);
@ -190,19 +190,19 @@ int32_t register_interrupt_type_handler(uint32_t type,
int32_t rc;
/* Validate the 'handler' parameter */
if (!handler)
if (handler == NULL)
return -EINVAL;
/* Validate the 'flags' parameter */
if (flags & INTR_TYPE_FLAGS_MASK)
if ((flags & INTR_TYPE_FLAGS_MASK) != 0U)
return -EINVAL;
/* Check if a handler has already been registered */
if (intr_type_descs[type].handler)
if (intr_type_descs[type].handler != NULL)
return -EALREADY;
rc = set_routing_model(type, flags);
if (rc)
if (rc != 0)
return rc;
/* Save the handler */
@ -218,7 +218,7 @@ int32_t register_interrupt_type_handler(uint32_t type,
******************************************************************************/
interrupt_type_handler_t get_interrupt_type_handler(uint32_t type)
{
if (validate_interrupt_type(type))
if (validate_interrupt_type(type) != 0)
return NULL;
return intr_type_descs[type].handler;

45
drivers/arm/cci/cci.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,11 +10,12 @@
#include <cci.h>
#include <debug.h>
#include <mmio.h>
#include <stdbool.h>
#include <stdint.h>
#define MAKE_CCI_PART_NUMBER(hi, lo) ((hi << 8) | lo)
#define CCI_PART_LO_MASK 0xff
#define CCI_PART_HI_MASK 0xf
#define MAKE_CCI_PART_NUMBER(hi, lo) (((hi) << 8) | (lo))
#define CCI_PART_LO_MASK U(0xff)
#define CCI_PART_HI_MASK U(0xf)
/* CCI part number codes read from Peripheral ID registers 0 and 1 */
#define CCI400_PART_NUM 0x420
@ -32,14 +33,14 @@ static const int *cci_slave_if_map;
static unsigned int max_master_id;
static int cci_num_slave_ports;
static int validate_cci_map(const int *map)
static bool validate_cci_map(const int *map)
{
unsigned int valid_cci_map = 0;
unsigned int valid_cci_map = 0U;
int slave_if_id;
int i;
unsigned int i;
/* Validate the map */
for (i = 0; i <= max_master_id; i++) {
for (i = 0U; i <= max_master_id; i++) {
slave_if_id = map[i];
if (slave_if_id < 0)
@ -47,22 +48,22 @@ static int validate_cci_map(const int *map)
if (slave_if_id >= cci_num_slave_ports) {
ERROR("Slave interface ID is invalid\n");
return 0;
return false;
}
if (valid_cci_map & (1 << slave_if_id)) {
if ((valid_cci_map & (1U << slave_if_id)) != 0U) {
ERROR("Multiple masters are assigned same slave interface ID\n");
return 0;
return false;
}
valid_cci_map |= 1 << slave_if_id;
valid_cci_map |= 1U << slave_if_id;
}
if (!valid_cci_map) {
if (valid_cci_map == 0U) {
ERROR("No master is assigned a valid slave interface\n");
return 0;
return false;
}
return 1;
return true;
}
/*
@ -108,8 +109,8 @@ static int get_slave_ports(unsigned int part_num)
void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters)
{
assert(map);
assert(base);
assert(map != NULL);
assert(base != 0U);
cci_base = base;
cci_slave_if_map = map;
@ -119,7 +120,7 @@ void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters)
* Master Id's are assigned from zero, So in an array of size n
* the max master id is (n - 1).
*/
max_master_id = num_cci_masters - 1;
max_master_id = num_cci_masters - 1U;
cci_num_slave_ports = get_slave_ports(read_cci_part_number(base));
#endif
assert(cci_num_slave_ports >= 0);
@ -133,7 +134,7 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id)
assert(master_id <= max_master_id);
assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0));
assert(cci_base);
assert(cci_base != 0U);
/*
* Enable Snoops and DVM messages, no need for Read/Modify/Write as
@ -150,7 +151,7 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id)
dsbish();
/* Wait for the dust to settle down */
while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U)
;
}
@ -160,7 +161,7 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id)
assert(master_id <= max_master_id);
assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0));
assert(cci_base);
assert(cci_base != 0U);
/*
* Disable Snoops and DVM messages, no need for Read/Modify/Write as
@ -177,7 +178,7 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id)
dsbish();
/* Wait for the dust to settle down */
while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT)
while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U)
;
}

19
drivers/arm/smmu/smmu_v3.c
View File

@ -1,15 +1,12 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <mmio.h>
#include <smmu_v3.h>
/* Test for pending invalidate */
#define INVAL_PENDING(_base) \
smmuv3_read_s_init(_base) & SMMU_S_INIT_INV_ALL_MASK
#include <stdbool.h>
static inline uint32_t smmuv3_read_s_idr1(uintptr_t base)
{
@ -26,6 +23,12 @@ static inline void smmuv3_write_s_init(uintptr_t base, uint32_t value)
mmio_write_32(base + SMMU_S_INIT, value);
}
/* Test for pending invalidate */
static inline bool smmuv3_inval_pending(uintptr_t base)
{
return (smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK) != 0U;
}
/*
* Initialize the SMMU by invalidating all secure caches and TLBs.
*
@ -41,14 +44,14 @@ int smmuv3_init(uintptr_t smmu_base)
* SMMU_S_INIT register is accessed.
*/
idr1_reg = smmuv3_read_s_idr1(smmu_base);
if (!((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) &
SMMU_S_IDR1_SECURE_IMPL_MASK)) {
if (((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) &
SMMU_S_IDR1_SECURE_IMPL_MASK) == 0U) {
return -1;
}
/* Initiate invalidation, and wait for it to finish */
smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK);
while (INVAL_PENDING(smmu_base))
while (smmuv3_inval_pending(smmu_base))
;
return 0;

2
include/bl31/ehf.h
View File

@ -14,7 +14,7 @@
#include <utils_def.h>
/* Valid priorities set bit 0 of the priority handler. */
#define EHF_PRI_VALID_ (((uintptr_t) 1) << 0)
#define EHF_PRI_VALID_ BIT(0)
/* Marker for no handler registered for a valid priority */
#define EHF_NO_HANDLER_ (0U | EHF_PRI_VALID_)

73
include/bl31/interrupt_mgmt.h
View File

@ -8,6 +8,7 @@
#define __INTERRUPT_MGMT_H__
#include <arch.h>
#include <utils_def.h>
/*******************************************************************************
* Constants for the types of interrupts recognised by the IM framework
@ -66,34 +67,6 @@
#define set_interrupt_rm_flag(flag, ss) ((flag) |= U(1) << (ss))
#define clr_interrupt_rm_flag(flag, ss) ((flag) &= ~(U(1) << (ss)))
/*******************************************************************************
* Macros to validate the routing model bits in the 'flags' for a type
* of interrupt. If the model does not match one of the valid masks
* -EINVAL is returned.
******************************************************************************/
#define validate_sel1_interrupt_rm(x) ((x) == INTR_SEL1_VALID_RM0 ? 0 : \
((x) == INTR_SEL1_VALID_RM1 ? 0 :\
-EINVAL))
#define validate_ns_interrupt_rm(x) ((x) == INTR_NS_VALID_RM0 ? 0 : \
((x) == INTR_NS_VALID_RM1 ? 0 :\
-EINVAL))
#if EL3_EXCEPTION_HANDLING
/*
* With EL3 exception handling, EL3 interrupts are always routed to EL3 from
* both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is the only
* valid routing model.
*/
#define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM1 ? 0 : \
-EINVAL)
#else
#define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM0 ? 0 : \
((x) == INTR_EL3_VALID_RM1 ? 0 :\
-EINVAL))
#endif
/*******************************************************************************
* Macros to set the 'flags' parameter passed to an interrupt type handler. Only
* the flag to indicate the security state when the exception was generated is
@ -108,9 +81,51 @@
#ifndef __ASSEMBLY__
#include <errno.h>
#include <stdint.h>
/* Prototype for defining a handler for an interrupt type */
/*******************************************************************************
* Helpers to validate the routing model bits in the 'flags' for a type
* of interrupt. If the model does not match one of the valid masks
* -EINVAL is returned.
******************************************************************************/
static inline int32_t validate_sel1_interrupt_rm(uint32_t x)
{
if ((x == INTR_SEL1_VALID_RM0) || (x == INTR_SEL1_VALID_RM1))
return 0;
return -EINVAL;
}
static inline int32_t validate_ns_interrupt_rm(uint32_t x)
{
if ((x == INTR_NS_VALID_RM0) || (x == INTR_NS_VALID_RM1))
return 0;
return -EINVAL;
}
static inline int32_t validate_el3_interrupt_rm(uint32_t x)
{
#if EL3_EXCEPTION_HANDLING
/*
* With EL3 exception handling, EL3 interrupts are always routed to EL3
* from both Secure and Non-secure, and therefore INTR_EL3_VALID_RM1 is
* the only valid routing model.
*/
if (x == INTR_EL3_VALID_RM1)
return 0;
#else
if ((x == INTR_EL3_VALID_RM0) || (x == INTR_EL3_VALID_RM1))
return 0;
#endif
return -EINVAL;
}
/*******************************************************************************
* Prototype for defining a handler for an interrupt type
******************************************************************************/
typedef uint64_t (*interrupt_type_handler_t)(uint32_t id,
uint32_t flags,
void *handle,

23
include/common/param_header.h
View File

@ -7,25 +7,28 @@
#ifndef __PARAM_HEADER_H__
#define __PARAM_HEADER_H__
#include <stdbool.h>
#include <utils_def.h>
/* Param header types */
#define PARAM_EP 0x01
#define PARAM_IMAGE_BINARY 0x02
#define PARAM_BL31 0x03
#define PARAM_BL_LOAD_INFO 0x04
#define PARAM_BL_PARAMS 0x05
#define PARAM_PSCI_LIB_ARGS 0x06
#define PARAM_SP_IMAGE_BOOT_INFO 0x07
#define PARAM_EP U(0x01)
#define PARAM_IMAGE_BINARY U(0x02)
#define PARAM_BL31 U(0x03)
#define PARAM_BL_LOAD_INFO U(0x04)
#define PARAM_BL_PARAMS U(0x05)
#define PARAM_PSCI_LIB_ARGS U(0x06)
#define PARAM_SP_IMAGE_BOOT_INFO U(0x07)
/* Param header version */
#define VERSION_1 0x01
#define VERSION_2 0x02
#define VERSION_1 U(0x01)
#define VERSION_2 U(0x02)
#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \
(_p)->h.type = (uint8_t)(_type); \
(_p)->h.version = (uint8_t)(_ver); \
(_p)->h.size = (uint16_t)sizeof(*(_p)); \
(_p)->h.attr = (uint32_t)(_attr) ; \
} while (0)
} while (false)
/* Following is used for populating structure members statically. */
#define SET_STATIC_PARAM_HEAD(_p, _type, _ver, _p_type, _attr) \

60
include/common/tbbr/tbbr_img_def.h
View File

@ -7,75 +7,77 @@
#ifndef __TBBR_IMG_DEF_H__
#define __TBBR_IMG_DEF_H__
#include <utils_def.h>
/* Firmware Image Package */
#define FIP_IMAGE_ID 0
#define FIP_IMAGE_ID U(0)
/* Trusted Boot Firmware BL2 */
#define BL2_IMAGE_ID 1
#define BL2_IMAGE_ID U(1)
/* SCP Firmware SCP_BL2 */
#define SCP_BL2_IMAGE_ID 2
#define SCP_BL2_IMAGE_ID U(2)
/* EL3 Runtime Firmware BL31 */
#define BL31_IMAGE_ID 3
#define BL31_IMAGE_ID U(3)
/* Secure Payload BL32 (Trusted OS) */
#define BL32_IMAGE_ID 4
#define BL32_IMAGE_ID U(4)
/* Non-Trusted Firmware BL33 */
#define BL33_IMAGE_ID 5
#define BL33_IMAGE_ID U(5)
/* Certificates */
#define TRUSTED_BOOT_FW_CERT_ID 6
#define TRUSTED_KEY_CERT_ID 7
#define TRUSTED_BOOT_FW_CERT_ID U(6)
#define TRUSTED_KEY_CERT_ID U(7)
#define SCP_FW_KEY_CERT_ID 8
#define SOC_FW_KEY_CERT_ID 9
#define TRUSTED_OS_FW_KEY_CERT_ID 10
#define NON_TRUSTED_FW_KEY_CERT_ID 11
#define SCP_FW_KEY_CERT_ID U(8)
#define SOC_FW_KEY_CERT_ID U(9)
#define TRUSTED_OS_FW_KEY_CERT_ID U(10)
#define NON_TRUSTED_FW_KEY_CERT_ID U(11)
#define SCP_FW_CONTENT_CERT_ID 12
#define SOC_FW_CONTENT_CERT_ID 13
#define TRUSTED_OS_FW_CONTENT_CERT_ID 14
#define NON_TRUSTED_FW_CONTENT_CERT_ID 15
#define SCP_FW_CONTENT_CERT_ID U(12)
#define SOC_FW_CONTENT_CERT_ID U(13)
#define TRUSTED_OS_FW_CONTENT_CERT_ID U(14)
#define NON_TRUSTED_FW_CONTENT_CERT_ID U(15)
/* Non-Trusted ROM Firmware NS_BL1U */
#define NS_BL1U_IMAGE_ID 16
#define NS_BL1U_IMAGE_ID U(16)
/* Trusted FWU Certificate */
#define FWU_CERT_ID 17
#define FWU_CERT_ID U(17)
/* Trusted FWU SCP Firmware SCP_BL2U */
#define SCP_BL2U_IMAGE_ID 18
#define SCP_BL2U_IMAGE_ID U(18)
/* Trusted FWU Boot Firmware BL2U */
#define BL2U_IMAGE_ID 19
#define BL2U_IMAGE_ID U(19)
/* Non-Trusted FWU Firmware NS_BL2U */
#define NS_BL2U_IMAGE_ID 20
#define NS_BL2U_IMAGE_ID U(20)
/* Secure Payload BL32_EXTRA1 (Trusted OS Extra1) */
#define BL32_EXTRA1_IMAGE_ID 21
#define BL32_EXTRA1_IMAGE_ID U(21)
/* Secure Payload BL32_EXTRA2 (Trusted OS Extra2) */
#define BL32_EXTRA2_IMAGE_ID 22
#define BL32_EXTRA2_IMAGE_ID U(22)
/* HW_CONFIG (e.g. Kernel DT) */
#define HW_CONFIG_ID 23
#define HW_CONFIG_ID U(23)
/* TB_FW_CONFIG */
#define TB_FW_CONFIG_ID 24
#define TB_FW_CONFIG_ID U(24)
/* SOC_FW_CONFIG */
#define SOC_FW_CONFIG_ID 25
#define SOC_FW_CONFIG_ID U(25)
/* TOS_FW_CONFIG */
#define TOS_FW_CONFIG_ID 26
#define TOS_FW_CONFIG_ID U(26)
/* NT_FW_CONFIG */
#define NT_FW_CONFIG_ID 27
#define NT_FW_CONFIG_ID U(27)
/* Define size of the array */
#define MAX_NUMBER_IDS 28
#define MAX_NUMBER_IDS U(28)
#endif /* __TBBR_IMG_DEF_H__ */

140
include/drivers/arm/cci.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,94 +7,96 @@
#ifndef __CCI_H__
#define __CCI_H__
#include <utils_def.h>
/* Slave interface offsets from PERIPHBASE */
#define SLAVE_IFACE6_OFFSET 0x7000
#define SLAVE_IFACE5_OFFSET 0x6000
#define SLAVE_IFACE4_OFFSET 0x5000
#define SLAVE_IFACE3_OFFSET 0x4000
#define SLAVE_IFACE2_OFFSET 0x3000
#define SLAVE_IFACE1_OFFSET 0x2000
#define SLAVE_IFACE0_OFFSET 0x1000
#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
(0x1000 * (index)))
#define SLAVE_IFACE6_OFFSET UL(0x7000)
#define SLAVE_IFACE5_OFFSET UL(0x6000)
#define SLAVE_IFACE4_OFFSET UL(0x5000)
#define SLAVE_IFACE3_OFFSET UL(0x4000)
#define SLAVE_IFACE2_OFFSET UL(0x3000)
#define SLAVE_IFACE1_OFFSET UL(0x2000)
#define SLAVE_IFACE0_OFFSET UL(0x1000)
#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
(UL(0x1000) * (index)))
/* Slave interface event and count register offsets from PERIPHBASE */
#define EVENT_SELECT7_OFFSET 0x80000
#define EVENT_SELECT6_OFFSET 0x70000
#define EVENT_SELECT5_OFFSET 0x60000
#define EVENT_SELECT4_OFFSET 0x50000
#define EVENT_SELECT3_OFFSET 0x40000
#define EVENT_SELECT2_OFFSET 0x30000
#define EVENT_SELECT1_OFFSET 0x20000
#define EVENT_SELECT0_OFFSET 0x10000
#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \
(0x10000 * (index)))
#define EVENT_SELECT7_OFFSET UL(0x80000)
#define EVENT_SELECT6_OFFSET UL(0x70000)
#define EVENT_SELECT5_OFFSET UL(0x60000)
#define EVENT_SELECT4_OFFSET UL(0x50000)
#define EVENT_SELECT3_OFFSET UL(0x40000)
#define EVENT_SELECT2_OFFSET UL(0x30000)
#define EVENT_SELECT1_OFFSET UL(0x20000)
#define EVENT_SELECT0_OFFSET UL(0x10000)
#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \
(UL(0x10000) * (index)))
/* Control and ID register offsets */
#define CTRL_OVERRIDE_REG 0x0
#define SECURE_ACCESS_REG 0x8
#define STATUS_REG 0xc
#define IMPRECISE_ERR_REG 0x10
#define PERFMON_CTRL_REG 0x100
#define IFACE_MON_CTRL_REG 0x104
#define CTRL_OVERRIDE_REG U(0x0)
#define SECURE_ACCESS_REG U(0x8)
#define STATUS_REG U(0xc)
#define IMPRECISE_ERR_REG U(0x10)
#define PERFMON_CTRL_REG U(0x100)
#define IFACE_MON_CTRL_REG U(0x104)
/* Component and peripheral ID registers */
#define PERIPHERAL_ID0 0xFE0
#define PERIPHERAL_ID1 0xFE4
#define PERIPHERAL_ID2 0xFE8
#define PERIPHERAL_ID3 0xFEC
#define PERIPHERAL_ID4 0xFD0
#define PERIPHERAL_ID5 0xFD4
#define PERIPHERAL_ID6 0xFD8
#define PERIPHERAL_ID7 0xFDC
#define PERIPHERAL_ID0 U(0xFE0)
#define PERIPHERAL_ID1 U(0xFE4)
#define PERIPHERAL_ID2 U(0xFE8)
#define PERIPHERAL_ID3 U(0xFEC)
#define PERIPHERAL_ID4 U(0xFD0)
#define PERIPHERAL_ID5 U(0xFD4)
#define PERIPHERAL_ID6 U(0xFD8)
#define PERIPHERAL_ID7 U(0xFDC)
#define COMPONENT_ID0 0xFF0
#define COMPONENT_ID1 0xFF4
#define COMPONENT_ID2 0xFF8
#define COMPONENT_ID3 0xFFC
#define COMPONENT_ID4 0x1000
#define COMPONENT_ID5 0x1004
#define COMPONENT_ID6 0x1008
#define COMPONENT_ID7 0x100C
#define COMPONENT_ID0 U(0xFF0)
#define COMPONENT_ID1 U(0xFF4)
#define COMPONENT_ID2 U(0xFF8)
#define COMPONENT_ID3 U(0xFFC)
#define COMPONENT_ID4 U(0x1000)
#define COMPONENT_ID5 U(0x1004)
#define COMPONENT_ID6 U(0x1008)
#define COMPONENT_ID7 U(0x100C)
/* Slave interface register offsets */
#define SNOOP_CTRL_REG 0x0
#define SH_OVERRIDE_REG 0x4
#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100
#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104
#define MAX_OT_REG 0x110
#define SNOOP_CTRL_REG U(0x0)
#define SH_OVERRIDE_REG U(0x4)
#define READ_CHNL_QOS_VAL_OVERRIDE_REG U(0x100)
#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG U(0x104)
#define MAX_OT_REG U(0x110)
/* Snoop Control register bit definitions */
#define DVM_EN_BIT (1 << 1)
#define SNOOP_EN_BIT (1 << 0)
#define SUPPORT_SNOOPS (1 << 30)
#define SUPPORT_DVM (1 << 31)
#define DVM_EN_BIT BIT_32(1)
#define SNOOP_EN_BIT BIT_32(0)
#define SUPPORT_SNOOPS BIT_32(30)
#define SUPPORT_DVM BIT_32(31)
/* Status register bit definitions */
#define CHANGE_PENDING_BIT (1 << 0)
#define CHANGE_PENDING_BIT BIT_32(0)
/* Event and count register offsets */
#define EVENT_SELECT_REG 0x0
#define EVENT_COUNT_REG 0x4
#define COUNT_CNTRL_REG 0x8
#define COUNT_OVERFLOW_REG 0xC
#define EVENT_SELECT_REG U(0x0)
#define EVENT_COUNT_REG U(0x4)
#define COUNT_CNTRL_REG U(0x8)
#define COUNT_OVERFLOW_REG U(0xC)
/* Slave interface monitor registers */
#define INT_MON_REG_SI0 0x90000
#define INT_MON_REG_SI1 0x90004
#define INT_MON_REG_SI2 0x90008
#define INT_MON_REG_SI3 0x9000C
#define INT_MON_REG_SI4 0x90010
#define INT_MON_REG_SI5 0x90014
#define INT_MON_REG_SI6 0x90018
#define INT_MON_REG_SI0 U(0x90000)
#define INT_MON_REG_SI1 U(0x90004)
#define INT_MON_REG_SI2 U(0x90008)
#define INT_MON_REG_SI3 U(0x9000C)
#define INT_MON_REG_SI4 U(0x90010)
#define INT_MON_REG_SI5 U(0x90014)
#define INT_MON_REG_SI6 U(0x90018)
/* Master interface monitor registers */
#define INT_MON_REG_MI0 0x90100
#define INT_MON_REG_MI1 0x90104
#define INT_MON_REG_MI2 0x90108
#define INT_MON_REG_MI3 0x9010c
#define INT_MON_REG_MI4 0x90110
#define INT_MON_REG_MI5 0x90114
#define INT_MON_REG_MI0 U(0x90100)
#define INT_MON_REG_MI1 U(0x90104)
#define INT_MON_REG_MI2 U(0x90108)
#define INT_MON_REG_MI3 U(0x9010c)
#define INT_MON_REG_MI4 U(0x90110)
#define INT_MON_REG_MI5 U(0x90114)
#define SLAVE_IF_UNUSED -1

11
include/drivers/arm/smmu_v3.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,18 +7,19 @@
#ifndef __SMMU_V3_H__
#define __SMMU_V3_H__
#include <utils_def.h>
#include <stdint.h>
/* SMMUv3 register offsets from device base */
#define SMMU_S_IDR1 0x8004
#define SMMU_S_INIT 0x803c
#define SMMU_S_IDR1 U(0x8004)
#define SMMU_S_INIT U(0x803c)
/* SMMU_S_IDR1 register fields */
#define SMMU_S_IDR1_SECURE_IMPL_SHIFT 31
#define SMMU_S_IDR1_SECURE_IMPL_MASK 0x1
#define SMMU_S_IDR1_SECURE_IMPL_MASK U(0x1)
/* SMMU_S_INIT register fields */
#define SMMU_S_INIT_INV_ALL_MASK 0x1
#define SMMU_S_INIT_INV_ALL_MASK U(0x1)
int smmuv3_init(uintptr_t smmu_base);

30
include/plat/arm/common/arm_config.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,19 +9,21 @@
#include <stdint.h>
#include <utils_def.h>
enum arm_config_flags {
/* Whether Base memory map is in use */
ARM_CONFIG_BASE_MMAP = BIT(1),
/* Whether TZC should be configured */
ARM_CONFIG_HAS_TZC = BIT(2),
/* FVP model has shifted affinity */
ARM_CONFIG_FVP_SHIFTED_AFF = BIT(3),
/* FVP model has SMMUv3 affinity */
ARM_CONFIG_FVP_HAS_SMMUV3 = BIT(4),
/* FVP model has CCI (400 or 500/550) devices */
ARM_CONFIG_FVP_HAS_CCI400 = BIT(5),
ARM_CONFIG_FVP_HAS_CCI5XX = BIT(6),
};
/* Whether Base memory map is in use */
#define ARM_CONFIG_BASE_MMAP BIT(1)
/* Whether TZC should be configured */
#define ARM_CONFIG_HAS_TZC BIT(2)
/* FVP model has shifted affinity */
#define ARM_CONFIG_FVP_SHIFTED_AFF BIT(3)
/* FVP model has SMMUv3 affinity */
#define ARM_CONFIG_FVP_HAS_SMMUV3 BIT(4)
/* FVP model has CCI (400 or 500/550) devices */
#define ARM_CONFIG_FVP_HAS_CCI400 BIT(5)
#define ARM_CONFIG_FVP_HAS_CCI5XX BIT(6)
typedef struct arm_config {
unsigned long flags;

2
plat/arm/board/fvp/fvp_bl31_setup.c
View File

@ -34,6 +34,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
fvp_interconnect_enable();
/* On FVP RevC, intialize SMMUv3 */
if (arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3)
if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
smmuv3_init(PLAT_FVP_SMMUV3_BASE);
}

12
plat/arm/common/arm_bl31_setup.c
View File

@ -16,8 +16,6 @@
#include <platform.h>
#include <ras.h>
#define BL31_END (uintptr_t)(&__BL31_END__)
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
@ -152,7 +150,7 @@ void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_con
* Copy BL33 and BL32 (if present), entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
while (bl_params) {
while (bl_params != NULL) {
if (bl_params->image_id == BL32_IMAGE_ID)
bl32_image_ep_info = *bl_params->ep_info;
@ -162,7 +160,7 @@ void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_con
bl_params = bl_params->next_params_info;
}
if (bl33_image_ep_info.pc == 0)
if (bl33_image_ep_info.pc == 0U)
panic();
# else /* LOAD_IMAGE_V2 */
@ -175,8 +173,8 @@ void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_con
assert(from_bl2->h.version >= VERSION_1);
/* Dynamic Config is not supported for LOAD_IMAGE_V1 */
assert(soc_fw_config == 0);
assert(hw_config == 0);
assert(soc_fw_config == 0U);
assert(hw_config == 0U);
/*
* Copy BL32 (if populated by BL2) and BL33 entry point information.
@ -236,7 +234,7 @@ void arm_bl31_platform_setup(void)
/* Enable and initialize the System level generic timer */
mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
CNTCR_FCREQ(0) | CNTCR_EN);
CNTCR_FCREQ(0U) | CNTCR_EN);
/* Allow access to the System counter timer module */
arm_configure_sys_timer();

5
plat/arm/common/sp_min/arm_sp_min_setup.c
View File

@ -5,6 +5,7 @@
*/
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <mmio.h>
@ -13,8 +14,6 @@
#include <platform_def.h>
#include <platform_sp_min.h>
#define BL32_END (uintptr_t)(&__BL32_END__)
static entry_point_info_t bl33_image_ep_info;
/* Weak definitions may be overridden in specific ARM standard platform */
@ -181,7 +180,7 @@ void sp_min_platform_setup(void)
/* Enable and initialize the System level generic timer */
mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
CNTCR_FCREQ(0) | CNTCR_EN);
CNTCR_FCREQ(0U) | CNTCR_EN);
/* Allow access to the System counter timer module */
arm_configure_sys_timer();

5
plat/layerscape/common/ls_bl31_setup.c
View File

@ -5,6 +5,7 @@
*/
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <mmio.h>
#include <gicv2.h>
@ -12,8 +13,6 @@
#include "plat_ls.h"
#include "soc.h"
#define BL31_END (uintptr_t)(&__BL31_END__)
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.
@ -168,7 +167,7 @@ void ls_bl31_platform_setup(void)
/* Enable and initialize the System level generic timer */
mmio_write_32(LS1043_SYS_CNTCTL_BASE + CNTCR_OFF,
CNTCR_FCREQ(0) | CNTCR_EN);
CNTCR_FCREQ(0U) | CNTCR_EN);
VERBOSE("Leave arm_bl31_platform_setup\n");
}

2
plat/socionext/synquacer/sq_bl31_setup.c
View File

@ -137,7 +137,7 @@ void bl31_platform_setup(void)
/* Enable and initialize the System level generic timer */
mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF,
CNTCR_FCREQ(0) | CNTCR_EN);
CNTCR_FCREQ(0U) | CNTCR_EN);
/* Allow access to the System counter timer module */
sq_configure_sys_timer();

5
plat/socionext/uniphier/uniphier_bl31_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -17,7 +17,6 @@
#include "uniphier.h"
#define BL31_END (unsigned long)(&__BL31_END__)
#define BL31_SIZE ((BL31_END) - (BL31_BASE))
static entry_point_info_t bl32_image_ep_info;
@ -70,7 +69,7 @@ void bl31_platform_setup(void)
/* Enable and initialize the System level generic timer */
mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
CNTCR_FCREQ(0) | CNTCR_EN);
CNTCR_FCREQ(0U) | CNTCR_EN);
}
void bl31_plat_arch_setup(void)