nxp: psci platform functions used by lib/psci
Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I9853263ed38fb2a9f04b9dc7d768942e32074719
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/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_PSCI_H
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#define PLAT_PSCI_H
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/* core abort current op */
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#define CORE_ABORT_OP 0x1
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/* psci power levels - these are actually affinity levels
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* in the psci_power_state_t array
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*/
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#define PLAT_CORE_LVL PSCI_CPU_PWR_LVL
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#define PLAT_CLSTR_LVL U(1)
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#define PLAT_SYS_LVL U(2)
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#define PLAT_MAX_LVL PLAT_SYS_LVL
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/* core state */
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/* OFF states 0x0 - 0xF */
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#define CORE_IN_RESET 0x0
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#define CORE_DISABLED 0x1
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#define CORE_OFF 0x2
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#define CORE_STANDBY 0x3
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#define CORE_PWR_DOWN 0x4
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#define CORE_WFE 0x6
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#define CORE_WFI 0x7
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#define CORE_LAST 0x8
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#define CORE_OFF_PENDING 0x9
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#define CORE_WORKING_INIT 0xA
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#define SYS_OFF_PENDING 0xB
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#define SYS_OFF 0xC
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/* ON states 0x10 - 0x1F */
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#define CORE_PENDING 0x10
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#define CORE_RELEASED 0x11
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#define CORE_WAKEUP 0x12
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/* highest off state */
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#define CORE_OFF_MAX 0xF
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/* lowest on state */
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#define CORE_ON_MIN CORE_PENDING
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#define DAIF_SET_MASK 0x3C0
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#define SCTLR_I_C_M_MASK 0x00001005
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#define SCTLR_C_MASK 0x00000004
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#define SCTLR_I_MASK 0x00001000
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#define CPUACTLR_L1PCTL_MASK 0x0000E000
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#define DCSR_RCPM2_BASE 0x20170000
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#define CPUECTLR_SMPEN_MASK 0x40
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#define CPUECTLR_SMPEN_EN 0x40
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#define CPUECTLR_RET_MASK 0x7
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#define CPUECTLR_RET_SET 0x2
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#define CPUECTLR_TIMER_MASK 0x7
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#define CPUECTLR_TIMER_8TICKS 0x2
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#define SCR_IRQ_MASK 0x2
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#define SCR_FIQ_MASK 0x4
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/* pwr mgmt features supported in the soc-specific code:
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* value == 0x0, the soc code does not support this feature
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* value != 0x0, the soc code supports this feature
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*/
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#define SOC_CORE_RELEASE 0x1
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#define SOC_CORE_RESTART 0x1
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#define SOC_CORE_OFF 0x1
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#define SOC_CORE_STANDBY 0x1
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#define SOC_CORE_PWR_DWN 0x1
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#define SOC_CLUSTER_STANDBY 0x1
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#define SOC_CLUSTER_PWR_DWN 0x1
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#define SOC_SYSTEM_STANDBY 0x1
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#define SOC_SYSTEM_PWR_DWN 0x1
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#define SOC_SYSTEM_OFF 0x1
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#define SOC_SYSTEM_RESET 0x1
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#define SOC_SYSTEM_RESET2 0x1
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#ifndef __ASSEMBLER__
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void __dead2 _psci_system_reset(void);
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void __dead2 _psci_system_off(void);
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int _psci_cpu_on(u_register_t core_mask);
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void _psci_cpu_prep_off(u_register_t core_mask);
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void __dead2 _psci_cpu_off_wfi(u_register_t core_mask,
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u_register_t wakeup_address);
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void __dead2 _psci_cpu_pwrdn_wfi(u_register_t core_mask,
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u_register_t wakeup_address);
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void __dead2 _psci_sys_pwrdn_wfi(u_register_t core_mask,
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u_register_t wakeup_address);
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void _psci_wakeup(u_register_t core_mask);
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void _psci_core_entr_stdby(u_register_t core_mask);
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void _psci_core_prep_stdby(u_register_t core_mask);
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void _psci_core_exit_stdby(u_register_t core_mask);
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void _psci_core_prep_pwrdn(u_register_t core_mask);
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void _psci_core_exit_pwrdn(u_register_t core_mask);
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void _psci_clstr_prep_stdby(u_register_t core_mask);
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void _psci_clstr_exit_stdby(u_register_t core_mask);
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void _psci_clstr_prep_pwrdn(u_register_t core_mask);
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void _psci_clstr_exit_pwrdn(u_register_t core_mask);
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void _psci_sys_prep_stdby(u_register_t core_mask);
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void _psci_sys_exit_stdby(u_register_t core_mask);
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void _psci_sys_prep_pwrdn(u_register_t core_mask);
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void _psci_sys_exit_pwrdn(u_register_t core_mask);
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#endif
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#endif /* __PLAT_PSCI_H__ */
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/*
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* Copyright 2018-2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <common/debug.h>
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#include <plat_gic.h>
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#include <plat_common.h>
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#include <plat_psci.h>
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#ifdef NXP_WARM_BOOT
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#include <plat_warm_rst.h>
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#endif
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#include <platform_def.h>
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#if (SOC_CORE_OFF || SOC_CORE_PWR_DWN)
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static void __dead2 _no_return_wfi(void)
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{
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_bl31_dead_wfi:
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wfi();
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goto _bl31_dead_wfi;
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}
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#endif
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#if (SOC_CORE_RELEASE || SOC_CORE_PWR_DWN)
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/* the entry for core warm boot */
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static uintptr_t warmboot_entry = (uintptr_t) NULL;
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#endif
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#if (SOC_CORE_RELEASE)
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static int _pwr_domain_on(u_register_t mpidr)
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{
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int core_pos = plat_core_pos(mpidr);
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int rc = PSCI_E_INVALID_PARAMS;
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u_register_t core_mask;
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if (core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT) {
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_soc_set_start_addr(warmboot_entry);
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dsb();
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isb();
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core_mask = (1 << core_pos);
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rc = _psci_cpu_on(core_mask);
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}
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return (rc);
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}
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#endif
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#if (SOC_CORE_OFF)
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static void _pwr_domain_off(const psci_power_state_t *target_state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state = _getCoreState(core_mask);
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/* set core state in internal data */
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core_state = CORE_OFF_PENDING;
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_setCoreState(core_mask, core_state);
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_psci_cpu_prep_off(core_mask);
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}
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#endif
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#if (SOC_CORE_OFF || SOC_CORE_PWR_DWN)
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static void __dead2 _pwr_down_wfi(const psci_power_state_t *target_state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state = _getCoreState(core_mask);
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switch (core_state) {
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#if (SOC_CORE_OFF)
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case CORE_OFF_PENDING:
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/* set core state in internal data */
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core_state = CORE_OFF;
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_setCoreState(core_mask, core_state);
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/* turn the core off */
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_psci_cpu_off_wfi(core_mask, warmboot_entry);
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break;
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#endif
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#if (SOC_CORE_PWR_DWN)
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case CORE_PWR_DOWN:
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/* power-down the core */
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_psci_cpu_pwrdn_wfi(core_mask, warmboot_entry);
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break;
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#endif
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#if (SOC_SYSTEM_PWR_DWN)
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case SYS_OFF_PENDING:
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/* set core state in internal data */
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core_state = SYS_OFF;
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_setCoreState(core_mask, core_state);
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/* power-down the system */
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_psci_sys_pwrdn_wfi(core_mask, warmboot_entry);
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break;
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#endif
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default:
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_no_return_wfi();
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break;
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}
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}
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#endif
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#if (SOC_CORE_RELEASE || SOC_CORE_RESTART)
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static void _pwr_domain_wakeup(const psci_power_state_t *target_state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state = _getCoreState(core_mask);
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switch (core_state) {
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case CORE_PENDING: /* this core is coming out of reset */
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/* soc per cpu setup */
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soc_init_percpu();
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/* gic per cpu setup */
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plat_gic_pcpu_init();
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/* set core state in internal data */
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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break;
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#if (SOC_CORE_RESTART)
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case CORE_WAKEUP:
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/* this core is waking up from OFF */
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_psci_wakeup(core_mask);
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/* set core state in internal data */
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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break;
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#endif
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}
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}
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#endif
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#if (SOC_CORE_STANDBY)
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static void _pwr_cpu_standby(plat_local_state_t cpu_state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state;
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if (cpu_state == PLAT_MAX_RET_STATE) {
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/* set core state to standby */
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core_state = CORE_STANDBY;
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_setCoreState(core_mask, core_state);
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_psci_core_entr_stdby(core_mask);
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/* when we are here, the core is waking up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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}
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}
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#endif
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#if (SOC_CORE_PWR_DWN)
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static void _pwr_suspend(const psci_power_state_t *state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state;
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if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) {
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#if (SOC_SYSTEM_PWR_DWN)
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_psci_sys_prep_pwrdn(core_mask);
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/* set core state */
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core_state = SYS_OFF_PENDING;
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_setCoreState(core_mask, core_state);
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#endif
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} else if (state->pwr_domain_state[PLAT_MAX_LVL]
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== PLAT_MAX_RET_STATE) {
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#if (SOC_SYSTEM_STANDBY)
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_psci_sys_prep_stdby(core_mask);
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/* set core state */
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core_state = CORE_STANDBY;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
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PLAT_MAX_OFF_STATE) {
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#if (SOC_CLUSTER_PWR_DWN)
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_psci_clstr_prep_pwrdn(core_mask);
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/* set core state */
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core_state = CORE_PWR_DOWN;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
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PLAT_MAX_RET_STATE) {
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#if (SOC_CLUSTER_STANDBY)
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_psci_clstr_prep_stdby(core_mask);
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/* set core state */
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core_state = CORE_STANDBY;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) {
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#if (SOC_CORE_PWR_DWN)
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/* prep the core for power-down */
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_psci_core_prep_pwrdn(core_mask);
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/* set core state */
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core_state = CORE_PWR_DOWN;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) {
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#if (SOC_CORE_STANDBY)
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_psci_core_prep_stdby(core_mask);
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/* set core state */
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core_state = CORE_STANDBY;
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_setCoreState(core_mask, core_state);
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#endif
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}
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}
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#endif
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#if (SOC_CORE_PWR_DWN)
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static void _pwr_suspend_finish(const psci_power_state_t *state)
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{
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u_register_t core_mask = plat_my_core_mask();
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u_register_t core_state;
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if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) {
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#if (SOC_SYSTEM_PWR_DWN)
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_psci_sys_exit_pwrdn(core_mask);
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/* when we are here, the core is back up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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} else if (state->pwr_domain_state[PLAT_MAX_LVL]
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== PLAT_MAX_RET_STATE) {
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#if (SOC_SYSTEM_STANDBY)
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_psci_sys_exit_stdby(core_mask);
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/* when we are here, the core is waking up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
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PLAT_MAX_OFF_STATE) {
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#if (SOC_CLUSTER_PWR_DWN)
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_psci_clstr_exit_pwrdn(core_mask);
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/* when we are here, the core is waking up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
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PLAT_MAX_RET_STATE) {
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#if (SOC_CLUSTER_STANDBY)
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_psci_clstr_exit_stdby(core_mask);
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/* when we are here, the core is waking up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) {
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#if (SOC_CORE_PWR_DWN)
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_psci_core_exit_pwrdn(core_mask);
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/* when we are here, the core is back up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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}
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else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) {
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#if (SOC_CORE_STANDBY)
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_psci_core_exit_stdby(core_mask);
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/* when we are here, the core is waking up
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* set core state to released
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*/
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core_state = CORE_RELEASED;
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_setCoreState(core_mask, core_state);
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#endif
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}
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}
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#endif
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#if (SOC_CORE_STANDBY || SOC_CORE_PWR_DWN)
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#define PWR_STATE_TYPE_MASK 0x00010000
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#define PWR_STATE_TYPE_STNDBY 0x0
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#define PWR_STATE_TYPE_PWRDWN 0x00010000
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#define PWR_STATE_LVL_MASK 0x03000000
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#define PWR_STATE_LVL_CORE 0x0
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#define PWR_STATE_LVL_CLSTR 0x01000000
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#define PWR_STATE_LVL_SYS 0x02000000
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#define PWR_STATE_LVL_MAX 0x03000000
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/* turns a requested power state into a target power state
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* based on SoC capabilities
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*/
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static int _pwr_state_validate(uint32_t pwr_state,
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psci_power_state_t *state)
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{
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int stat = PSCI_E_INVALID_PARAMS;
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int pwrdn = (pwr_state & PWR_STATE_TYPE_MASK);
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int lvl = (pwr_state & PWR_STATE_LVL_MASK);
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switch (lvl) {
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case PWR_STATE_LVL_MAX:
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if (pwrdn && SOC_SYSTEM_PWR_DWN)
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state->pwr_domain_state[PLAT_MAX_LVL] =
|
||||
PLAT_MAX_OFF_STATE;
|
||||
else if (SOC_SYSTEM_STANDBY)
|
||||
state->pwr_domain_state[PLAT_MAX_LVL] =
|
||||
PLAT_MAX_RET_STATE;
|
||||
/* intentional fall-thru condition */
|
||||
case PWR_STATE_LVL_SYS:
|
||||
if (pwrdn && SOC_SYSTEM_PWR_DWN)
|
||||
state->pwr_domain_state[PLAT_SYS_LVL] =
|
||||
PLAT_MAX_OFF_STATE;
|
||||
else if (SOC_SYSTEM_STANDBY)
|
||||
state->pwr_domain_state[PLAT_SYS_LVL] =
|
||||
PLAT_MAX_RET_STATE;
|
||||
/* intentional fall-thru condition */
|
||||
case PWR_STATE_LVL_CLSTR:
|
||||
if (pwrdn && SOC_CLUSTER_PWR_DWN)
|
||||
state->pwr_domain_state[PLAT_CLSTR_LVL] =
|
||||
PLAT_MAX_OFF_STATE;
|
||||
else if (SOC_CLUSTER_STANDBY)
|
||||
state->pwr_domain_state[PLAT_CLSTR_LVL] =
|
||||
PLAT_MAX_RET_STATE;
|
||||
/* intentional fall-thru condition */
|
||||
case PWR_STATE_LVL_CORE:
|
||||
stat = PSCI_E_SUCCESS;
|
||||
|
||||
if (pwrdn && SOC_CORE_PWR_DWN)
|
||||
state->pwr_domain_state[PLAT_CORE_LVL] =
|
||||
PLAT_MAX_OFF_STATE;
|
||||
else if (SOC_CORE_STANDBY)
|
||||
state->pwr_domain_state[PLAT_CORE_LVL] =
|
||||
PLAT_MAX_RET_STATE;
|
||||
break;
|
||||
}
|
||||
return (stat);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (SOC_SYSTEM_PWR_DWN)
|
||||
static void _pwr_state_sys_suspend(psci_power_state_t *req_state)
|
||||
{
|
||||
|
||||
/* if we need to have per-SoC settings, then we need to
|
||||
* extend this by calling into psci_utils.S and from there
|
||||
* on down to the SoC.S files
|
||||
*/
|
||||
|
||||
req_state->pwr_domain_state[PLAT_MAX_LVL] = PLAT_MAX_OFF_STATE;
|
||||
req_state->pwr_domain_state[PLAT_SYS_LVL] = PLAT_MAX_OFF_STATE;
|
||||
req_state->pwr_domain_state[PLAT_CLSTR_LVL] = PLAT_MAX_OFF_STATE;
|
||||
req_state->pwr_domain_state[PLAT_CORE_LVL] = PLAT_MAX_OFF_STATE;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(NXP_WARM_BOOT) && (SOC_SYSTEM_RESET2)
|
||||
static int psci_system_reset2(int is_vendor,
|
||||
int reset_type,
|
||||
u_register_t cookie)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
INFO("Executing the sequence of warm reset.\n");
|
||||
ret = prep_n_execute_warm_reset();
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static plat_psci_ops_t _psci_pm_ops = {
|
||||
#if (SOC_SYSTEM_OFF)
|
||||
.system_off = _psci_system_off,
|
||||
#endif
|
||||
#if (SOC_SYSTEM_RESET)
|
||||
.system_reset = _psci_system_reset,
|
||||
#endif
|
||||
#if defined(NXP_WARM_BOOT) && (SOC_SYSTEM_RESET2)
|
||||
.system_reset2 = psci_system_reset2,
|
||||
#endif
|
||||
#if (SOC_CORE_RELEASE || SOC_CORE_RESTART)
|
||||
/* core released or restarted */
|
||||
.pwr_domain_on_finish = _pwr_domain_wakeup,
|
||||
#endif
|
||||
#if (SOC_CORE_OFF)
|
||||
/* core shutting down */
|
||||
.pwr_domain_off = _pwr_domain_off,
|
||||
#endif
|
||||
#if (SOC_CORE_OFF || SOC_CORE_PWR_DWN)
|
||||
.pwr_domain_pwr_down_wfi = _pwr_down_wfi,
|
||||
#endif
|
||||
#if (SOC_CORE_STANDBY || SOC_CORE_PWR_DWN)
|
||||
/* cpu_suspend */
|
||||
.validate_power_state = _pwr_state_validate,
|
||||
#if (SOC_CORE_STANDBY)
|
||||
.cpu_standby = _pwr_cpu_standby,
|
||||
#endif
|
||||
#if (SOC_CORE_PWR_DWN)
|
||||
.pwr_domain_suspend = _pwr_suspend,
|
||||
.pwr_domain_suspend_finish = _pwr_suspend_finish,
|
||||
#endif
|
||||
#endif
|
||||
#if (SOC_SYSTEM_PWR_DWN)
|
||||
.get_sys_suspend_power_state = _pwr_state_sys_suspend,
|
||||
#endif
|
||||
#if (SOC_CORE_RELEASE)
|
||||
/* core executing psci_cpu_on */
|
||||
.pwr_domain_on = _pwr_domain_on
|
||||
#endif
|
||||
};
|
||||
|
||||
#if (SOC_CORE_RELEASE || SOC_CORE_PWR_DWN)
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
warmboot_entry = sec_entrypoint;
|
||||
*psci_ops = &_psci_pm_ops;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
*psci_ops = &_psci_pm_ops;
|
||||
return 0;
|
||||
}
|
||||
#endif
|
|
@ -0,0 +1,35 @@
|
|||
#
|
||||
# Copyright 2018-2020 NXP
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
#
|
||||
#------------------------------------------------------------------------------
|
||||
#
|
||||
# Select the PSCI files
|
||||
#
|
||||
# -----------------------------------------------------------------------------
|
||||
|
||||
ifeq (${ADD_PSCI},)
|
||||
|
||||
ADD_PSCI := 1
|
||||
PLAT_PSCI_PATH := $(PLAT_COMMON_PATH)/psci
|
||||
|
||||
PSCI_SOURCES := ${PLAT_PSCI_PATH}/plat_psci.c \
|
||||
${PLAT_PSCI_PATH}/$(ARCH)/psci_utils.S \
|
||||
plat/common/plat_psci_common.c
|
||||
|
||||
PLAT_INCLUDES += -I${PLAT_PSCI_PATH}/include
|
||||
|
||||
ifeq (${BL_COMM_PSCI_NEEDED},yes)
|
||||
BL_COMMON_SOURCES += ${PSCI_SOURCES}
|
||||
else
|
||||
ifeq (${BL2_PSCI_NEEDED},yes)
|
||||
BL2_SOURCES += ${PSCI_SOURCES}
|
||||
endif
|
||||
ifeq (${BL31_PSCI_NEEDED},yes)
|
||||
BL31_SOURCES += ${PSCI_SOURCES}
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
# -----------------------------------------------------------------------------
|
Loading…
Reference in New Issue