Merge pull request #920 from vwadekar/asserts-release-nvidia

Asserts release nvidia

plat/nvidia/tegra/common/drivers/smmu/smmu.c

@@ -89,7 +89,6 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
 {
 	uint32_t i, num_entries = 0;
 	smmu_regs_t *smmu_ctx_regs;
-#if DEBUG
 	plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
 	uint64_t tzdram_base = params_from_bl2->tzdram_base;
 	uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
@@ -102,8 +101,6 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
 	(1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
 
 	assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
-#endif
-
 	assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
 
 	/* get SMMU context table */

plat/nvidia/tegra/common/tegra_common.mk

@@ -28,19 +28,6 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
-CRASH_REPORTING		:=	1
-$(eval $(call add_define,CRASH_REPORTING))
-
-ASM_ASSERTION		:=	1
-$(eval $(call add_define,ASM_ASSERTION))
-
-USE_COHERENT_MEM	:=	0
-
-SEPARATE_CODE_AND_RODATA :=	1
-
-PLAT_XLAT_TABLES_DYNAMIC :=	1
-$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
-
 PLAT_INCLUDES		:=	-Iplat/nvidia/tegra/include/drivers \
 				-Iplat/nvidia/tegra/include \
 				-Iplat/nvidia/tegra/include/${TARGET_SOC}

plat/nvidia/tegra/platform.mk

@@ -30,12 +30,29 @@
 
 SOC_DIR			:=	plat/nvidia/tegra/soc/${TARGET_SOC}
 
-# Enable PSCI v1.0 extended state ID format
-PSCI_EXTENDED_STATE_ID	:=	1
+# dump the state on crash console
+CRASH_REPORTING		:=	1
+$(eval $(call add_define,CRASH_REPORTING))
+
+# enable assert() for release/debug builds
+ENABLE_ASSERTIONS	:=	1
 
 # Disable the PSCI platform compatibility layer
 ENABLE_PLAT_COMPAT	:=	0
 
+# enable dynamic memory mapping
+PLAT_XLAT_TABLES_DYNAMIC :=	1
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+
+# Enable PSCI v1.0 extended state ID format
+PSCI_EXTENDED_STATE_ID	:=	1
+
+# code and read-only data should be put on separate memory pages
+SEPARATE_CODE_AND_RODATA :=	1
+
+# do not use coherent memory
+USE_COHERENT_MEM	:=	0
+
 include plat/nvidia/tegra/common/tegra_common.mk
 include ${SOC_DIR}/platform_${TARGET_SOC}.mk
 

plat/nvidia/tegra/soc/t132/plat_psci_handlers.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -132,7 +132,7 @@ int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
 
 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 {
-#if DEBUG
+#if ENABLE_ASSERTIONS
 	int cpu = read_mpidr() & MPIDR_CPU_MASK;
 
 	/* SYSTEM_SUSPEND only on CPU0 */