From dd4a0d1618a6367061ab507ea450db98bbf2cc36 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 5 Aug 2019 16:40:35 +0200 Subject: [PATCH] rockchip: move dt-coreboot uart distinction into param handling code Rockchip platforms can be booted from either u-boot or coreboot. So far the Coreboot-console was initizalized from a coreboot data struct in the early_param2 callbacks and dt-based consoles with data from the rockchip_get_uart_* functions. But later code may also need this console information for example for special suspend handling. To make this easy follow a suggestion from Julius Werner and move the coreboot<->dt distinction into the rockchip_get_uart_* functions, thus making correct data about the used uart available to all Rockchip platform code at all times. This includes a new rockchip_get_uart_clock as well, because while the dt-platforms right now always just default the rate defined in a constant Coreboot provides its own field for the clock rate and we don't want to loose that information for the console init. Similarly the rk_uart_* variables should move into the non-Coreboot code, to prevent them from being marked as unused, which also requires the rk_get_uart_* functions to move below the actual dt-parsing. Signed-off-by: Heiko Stuebner Change-Id: I278d595d2aa6c6864187fc8979a9fbff9814feac --- plat/rockchip/common/bl31_plat_setup.c | 15 ++------ plat/rockchip/common/include/plat_private.h | 1 + plat/rockchip/common/params_setup.c | 42 +++++++++++++++------ plat/rockchip/common/sp_min_plat_setup.c | 16 +++----- 4 files changed, 40 insertions(+), 34 deletions(-) diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index b04c08a4f..c4a03592e 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -62,16 +61,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, params_early_setup(arg1); -#if COREBOOT - if (coreboot_serial.type) - console_16550_register(coreboot_serial.baseaddr, - coreboot_serial.input_hertz, - coreboot_serial.baud, - &console); -#else - console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK, - rockchip_get_uart_baudrate(), &console); -#endif + if (rockchip_get_uart_base() != 0) + console_16550_register(rockchip_get_uart_base(), + rockchip_get_uart_clock(), + rockchip_get_uart_baudrate(), &console); VERBOSE("bl31_setup\n"); diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h index f3303dbc7..98143b7f6 100644 --- a/plat/rockchip/common/include/plat_private.h +++ b/plat/rockchip/common/include/plat_private.h @@ -140,6 +140,7 @@ extern const mmap_region_t plat_rk_mmap[]; uint32_t rockchip_get_uart_base(void); uint32_t rockchip_get_uart_baudrate(void); +uint32_t rockchip_get_uart_clock(void); #endif /* __ASSEMBLY__ */ diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c index 9e8ef40ce..8c2e5e911 100644 --- a/plat/rockchip/common/params_setup.c +++ b/plat/rockchip/common/params_setup.c @@ -26,18 +26,6 @@ static struct bl_aux_gpio_info poweroff_gpio; static struct bl_aux_gpio_info suspend_gpio[10]; uint32_t suspend_gpio_cnt; static struct bl_aux_rk_apio_info suspend_apio; -static uint32_t rk_uart_base = PLAT_RK_UART_BASE; -static uint32_t rk_uart_baudrate = PLAT_RK_UART_BAUDRATE; - -uint32_t rockchip_get_uart_base(void) -{ - return rk_uart_base; -} - -uint32_t rockchip_get_uart_baudrate(void) -{ - return rk_uart_baudrate; -} #if COREBOOT static int dt_process_fdt(u_register_t param_from_bl2) @@ -45,6 +33,9 @@ static int dt_process_fdt(u_register_t param_from_bl2) return -ENODEV; } #else +static uint32_t rk_uart_base = PLAT_RK_UART_BASE; +static uint32_t rk_uart_baudrate = PLAT_RK_UART_BAUDRATE; +static uint32_t rk_uart_clock = PLAT_RK_UART_CLOCK; static uint8_t fdt_buffer[0x10000]; void *plat_get_fdt(void) @@ -154,6 +145,33 @@ static int dt_process_fdt(u_register_t param_from_bl2) } #endif +uint32_t rockchip_get_uart_base(void) +{ +#if COREBOOT + return coreboot_serial.baseaddr; +#else + return rk_uart_base; +#endif +} + +uint32_t rockchip_get_uart_baudrate(void) +{ +#if COREBOOT + return coreboot_serial.baud; +#else + return rk_uart_baudrate; +#endif +} + +uint32_t rockchip_get_uart_clock(void) +{ +#if COREBOOT + return coreboot_serial.input_hertz; +#else + return rk_uart_clock; +#endif +} + struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void) { return &rst_gpio; diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c index 7638dac56..6d15075f2 100644 --- a/plat/rockchip/common/sp_min_plat_setup.c +++ b/plat/rockchip/common/sp_min_plat_setup.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -57,16 +56,11 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, params_early_setup(arg1); -#if COREBOOT - if (coreboot_serial.type) - console_16550_register(coreboot_serial.baseaddr, - coreboot_serial.input_hertz, - coreboot_serial.baud, - &console); -#else - console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK, - rockchip_get_uart_baudrate(), &console); -#endif + if (rockchip_get_uart_base() != 0) + console_16550_register(rockchip_get_uart_base(), + rockchip_get_uart_clock(), + rockchip_get_uart_baudrate(), &console); + VERBOSE("sp_min_setup\n"); bl31_params_parse_helper(arg0, NULL, &bl33_ep_info);