NXP: TZC API to configure ddr region
NXP TZC-400 API(s) to configure ddr regions are based on: - drivers/arm/tzc Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I524433ff9fafe1170b13e99b7de01fe957b6d305
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Pankaj Gupta
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447a42e735
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <common/debug.h>
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#include <plat_tzc400.h>
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#pragma weak populate_tzc400_reg_list
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#ifdef DEFAULT_TZASC_CONFIG
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/*
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* Typical Memory map of DRAM0
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* |-----------NXP_NS_DRAM_ADDR ( = NXP_DRAM0_ADDR)----------|
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* | |
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* | |
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* | Non-SECURE REGION |
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* | |
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* | |
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* | |
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* |------- (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE - 1) -------|
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* |-----------------NXP_SECURE_DRAM_ADDR--------------------|
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* | |
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* | |
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* | |
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* | SECURE REGION (= 64MB) |
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* | |
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* | |
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* | |
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* |--- (NXP_SECURE_DRAM_ADDR + NXP_SECURE_DRAM_SIZE - 1)----|
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* |-----------------NXP_SP_SHRD_DRAM_ADDR-------------------|
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* | |
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* | Secure EL1 Payload SHARED REGION (= 2MB) |
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* | |
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* |-----------(NXP_DRAM0_ADDR + NXP_DRAM0_SIZE - 1)---------|
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*
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*
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*
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* Typical Memory map of DRAM1
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* |---------------------NXP_DRAM1_ADDR----------------------|
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* | |
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* | |
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* | Non-SECURE REGION |
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* | |
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* | |
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* |---(NXP_DRAM1_ADDR + Dynamically calculated Size - 1) ---|
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*
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*
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* Typical Memory map of DRAM2
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* |---------------------NXP_DRAM2_ADDR----------------------|
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* | |
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* | |
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* | Non-SECURE REGION |
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* | |
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* | |
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* |---(NXP_DRAM2_ADDR + Dynamically calculated Size - 1) ---|
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*/
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/*****************************************************************************
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* This function sets up access permissions on memory regions
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*
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* Input:
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* tzc400_reg_list : TZC400 Region List
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* dram_idx : DRAM index
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* list_idx : TZC400 Region List Index
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* dram_start_addr : Start address of DRAM at dram_idx.
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* dram_size : Size of DRAM at dram_idx.
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* secure_dram_sz : Secure DRAM Size
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* shrd_dram_sz : Shared DRAM Size
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*
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* Out:
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* list_idx : last populated index + 1
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*
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****************************************************************************/
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int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list,
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int dram_idx, int list_idx,
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uint64_t dram_start_addr,
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uint64_t dram_size,
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uint32_t secure_dram_sz,
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uint32_t shrd_dram_sz)
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{
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if (list_idx == 0) {
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/* No need to configure TZC Region 0 in this list.
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*/
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list_idx++;
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}
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/* Continue with list entries for index > 0 */
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if (dram_idx == 0) {
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/* TZC Region 1 on DRAM0 for Secure Memory*/
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tzc400_reg_list[list_idx].reg_filter_en = 1;
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tzc400_reg_list[list_idx].start_addr = dram_start_addr + dram_size;
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tzc400_reg_list[list_idx].end_addr = dram_start_addr + dram_size
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+ secure_dram_sz - 1;
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tzc400_reg_list[list_idx].sec_attr = TZC_REGION_S_RDWR;
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tzc400_reg_list[list_idx].nsaid_permissions = TZC_REGION_NS_NONE;
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list_idx++;
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/* TZC Region 2 on DRAM0 for Shared Memory*/
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tzc400_reg_list[list_idx].reg_filter_en = 1;
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tzc400_reg_list[list_idx].start_addr = dram_start_addr + dram_size
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+ secure_dram_sz;
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tzc400_reg_list[list_idx].end_addr = dram_start_addr + dram_size
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+ secure_dram_sz
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+ shrd_dram_sz
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- 1;
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tzc400_reg_list[list_idx].sec_attr = TZC_REGION_S_RDWR;
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tzc400_reg_list[list_idx].nsaid_permissions = TZC_NS_ACCESS_ID;
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list_idx++;
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/* TZC Region 3 on DRAM0 for Non-Secure Memory*/
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tzc400_reg_list[list_idx].reg_filter_en = 1;
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tzc400_reg_list[list_idx].start_addr = dram_start_addr;
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tzc400_reg_list[list_idx].end_addr = dram_start_addr + dram_size
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- 1;
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tzc400_reg_list[list_idx].sec_attr = TZC_REGION_S_RDWR;
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tzc400_reg_list[list_idx].nsaid_permissions = TZC_NS_ACCESS_ID;
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list_idx++;
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} else {
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/* TZC Region 3+i on DRAM(> 0) for Non-Secure Memory*/
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tzc400_reg_list[list_idx].reg_filter_en = 1;
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tzc400_reg_list[list_idx].start_addr = dram_start_addr;
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tzc400_reg_list[list_idx].end_addr = dram_start_addr + dram_size
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- 1;
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tzc400_reg_list[list_idx].sec_attr = TZC_REGION_S_RDWR;
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tzc400_reg_list[list_idx].nsaid_permissions = TZC_NS_ACCESS_ID;
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list_idx++;
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}
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return list_idx;
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}
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#else
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int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list,
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int dram_idx, int list_idx,
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uint64_t dram_start_addr,
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uint64_t dram_size,
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uint32_t secure_dram_sz,
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uint32_t shrd_dram_sz)
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{
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ERROR("tzc400_reg_list used is not a default list\n");
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ERROR("%s needs to be over-written.\n", __func__);
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return 0;
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}
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#endif /* DEFAULT_TZASC_CONFIG */
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/*******************************************************************************
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* Configure memory access permissions
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* - Region 0 with no access;
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* - Region 1 to 4 as per the tzc400_reg_list populated by
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* function populate_tzc400_reg_list() with default for all the SoC.
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******************************************************************************/
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void mem_access_setup(uintptr_t base, uint32_t total_regions,
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struct tzc400_reg *tzc400_reg_list)
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{
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uint32_t list_indx = 0U;
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INFO("Configuring TrustZone Controller\n");
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tzc400_init(base);
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/* Disable filters. */
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tzc400_disable_filters();
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/* Region 0 set to no access by default */
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tzc400_configure_region0(TZC_REGION_S_NONE, 0U);
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for (list_indx = 1U; list_indx < total_regions; list_indx++) {
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tzc400_configure_region(
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tzc400_reg_list[list_indx].reg_filter_en,
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list_indx,
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tzc400_reg_list[list_indx].start_addr,
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tzc400_reg_list[list_indx].end_addr,
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tzc400_reg_list[list_indx].sec_attr,
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tzc400_reg_list[list_indx].nsaid_permissions);
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}
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/*
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* Raise an exception if a NS device tries to access secure memory
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* TODO: Add interrupt handling support.
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*/
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tzc400_set_action(TZC_ACTION_ERR);
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/* Enable filters. */
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tzc400_enable_filters();
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}
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@ -0,0 +1,55 @@
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#if !defined(PLAT_TZC400_H) && defined(IMAGE_BL2)
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#define PLAT_TZC400_H
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#include <tzc400.h>
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/* Structure to configure TZC Regions' boundaries and attributes. */
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struct tzc400_reg {
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uint8_t reg_filter_en;
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unsigned long long start_addr;
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unsigned long long end_addr;
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unsigned int sec_attr;
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unsigned int nsaid_permissions;
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};
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#define TZC_REGION_NS_NONE 0x00000000U
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/* NXP Platforms do not support NS Access ID (NSAID) based non-secure access.
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* Supports only non secure through generic NS ACCESS ID
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*/
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#define TZC_NS_ACCESS_ID 0xFFFFFFFFU
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/* Number of DRAM regions to be configured
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* for the platform can be over-written.
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*
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* Array tzc400_reg_list too, needs be over-written
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* if there is any changes to default DRAM region
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* configuration.
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*/
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#ifndef MAX_NUM_TZC_REGION
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/* 3 regions:
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* Region 0(default),
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* Region 1 (DRAM0, Secure Memory),
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* Region 2 (DRAM0, Shared memory)
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*/
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#define MAX_NUM_TZC_REGION NUM_DRAM_REGIONS + 3
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#define DEFAULT_TZASC_CONFIG 1
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#endif
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void mem_access_setup(uintptr_t base, uint32_t total_regions,
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struct tzc400_reg *tzc400_reg_list);
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int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list,
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int dram_idx, int list_idx,
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uint64_t dram_start_addr,
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uint64_t dram_size,
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uint32_t secure_dram_sz,
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uint32_t shrd_dram_sz);
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#endif /* PLAT_TZC400_H */
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@ -0,0 +1,35 @@
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#
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# Copyright 2021 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ifeq (${ADD_TZASC},)
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ADD_TZASC := 1
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TZASC_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/tzc
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PLAT_INCLUDES += -I$(TZASC_DRIVERS_PATH)
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ifeq ($(TZC_ID), TZC400)
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TZASC_SOURCES += drivers/arm/tzc/tzc400.c\
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$(TZASC_DRIVERS_PATH)/plat_tzc400.c
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else ifeq ($(TZC_ID), NONE)
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$(info -> No TZC present on platform)
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else
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$(error -> TZC type not set!)
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endif
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ifeq (${BL_COMM_TZASC_NEEDED},yes)
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BL_COMMON_SOURCES += ${TZASC_SOURCES}
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else
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ifeq (${BL2_TZASC_NEEDED},yes)
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BL2_SOURCES += ${TZASC_SOURCES}
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endif
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ifeq (${BL31_TZASC_NEEDED},yes)
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BL31_SOURCES += ${TZASC_SOURCES}
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endif
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endif
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endif
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