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Merge changes from topic "ddr_map" into integration 

* changes:
  stm32mp1: use stm32mp_get_ddr_ns_size() function
  stm32mp1: set XN attribute for some areas in BL2
  stm32mp1: dynamically map DDR later and non-cacheable during its test
  stm32mp1: add a function to get non-secure DDR size
This commit is contained in:
Olivier Deprez 2020-03-30 15:27:32 +00:00 committed by TrustedFirmware Code Review
parent ee91cd2ed3 5813e6edbc
commit de8f9cd4cd
10 changed files with 99 additions and 51 deletions
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11
drivers/st/ddr/stm32mp1_ram.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@ -250,8 +250,9 @@ static int stm32mp1_ddr_setup(void)
VERBOSE("%s : ram size(%x, %x)\n", __func__,
(uint32_t)priv->info.base, (uint32_t)priv->info.size);
write_sctlr(read_sctlr() & ~SCTLR_C_BIT);
dcsw_op_all(DC_OP_CISW);
if (stm32mp_map_ddr_non_cacheable() != 0) {
panic();
}
uret = ddr_test_data_bus();
if (uret != 0U) {
@ -274,7 +275,9 @@ static int stm32mp1_ddr_setup(void)
panic();
}
write_sctlr(read_sctlr() | SCTLR_C_BIT);
if (stm32mp_unmap_ddr() != 0) {
panic();
}
return 0;
}

6
plat/st/common/include/stm32mp_common.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -87,4 +87,8 @@ void stm32mp_io_setup(void);
*/
int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer);
/* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */
int stm32mp_map_ddr_non_cacheable(void);
int stm32mp_unmap_ddr(void);
#endif /* STM32MP_COMMON_H */

16
plat/st/common/stm32mp_common.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -12,6 +12,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/st/stm32mp_clkfunc.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
uintptr_t plat_get_ns_image_entrypoint(void)
@ -151,3 +152,16 @@ int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer)
return 0;
}
int stm32mp_map_ddr_non_cacheable(void)
{
return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
STM32MP_DDR_MAX_SIZE,
MT_NON_CACHEABLE | MT_RW | MT_NS);
}
int stm32mp_unmap_ddr(void)
{
return mmap_remove_dynamic_region(STM32MP_DDR_BASE,
STM32MP_DDR_MAX_SIZE);
}

41
plat/st/stm32mp1/bl2_plat_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -130,6 +130,7 @@ void bl2_el3_early_platform_setup(u_register_t arg0,
void bl2_platform_setup(void)
{
int ret;
uint32_t ddr_ns_size;
if (dt_pmic_status() > 0) {
initialize_pmic();
@ -141,8 +142,24 @@ void bl2_platform_setup(void)
panic();
}
ddr_ns_size = stm32mp_get_ddr_ns_size();
assert(ddr_ns_size > 0U);
/* Map non secure DDR for BL33 load, now with cacheable attribute */
ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
ddr_ns_size, MT_MEMORY | MT_RW | MT_NS);
assert(ret == 0);
#ifdef AARCH32_SP_OPTEE
INFO("BL2 runs OP-TEE setup\n");
/* Map secure DDR for OP-TEE paged area */
ret = mmap_add_dynamic_region(STM32MP_DDR_BASE + ddr_ns_size,
STM32MP_DDR_BASE + ddr_ns_size,
STM32MP_DDR_S_SIZE,
MT_MEMORY | MT_RW | MT_SECURE);
assert(ret == 0);
/* Initialize tzc400 after DDR initialization */
stm32mp1_security_setup();
#else
@ -166,14 +183,6 @@ void bl2_el3_plat_arch_setup(void)
MT_CODE | MT_SECURE);
#ifdef AARCH32_SP_OPTEE
/* OP-TEE image needs post load processing: keep RAM read/write */
mmap_add_region(STM32MP_DDR_BASE + dt_get_ddr_size() -
STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE,
STM32MP_DDR_BASE + dt_get_ddr_size() -
STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE,
STM32MP_DDR_S_SIZE,
MT_MEMORY | MT_RW | MT_SECURE);
mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
STM32MP_OPTEE_SIZE,
MT_MEMORY | MT_RW | MT_SECURE);
@ -181,19 +190,12 @@ void bl2_el3_plat_arch_setup(void)
/* Prevent corruption of preloaded BL32 */
mmap_add_region(BL32_BASE, BL32_BASE,
BL32_LIMIT - BL32_BASE,
MT_MEMORY | MT_RO | MT_SECURE);
MT_RO_DATA | MT_SECURE);
#endif
/* Map non secure DDR for BL33 load and DDR training area restore */
mmap_add_region(STM32MP_DDR_BASE,
STM32MP_DDR_BASE,
STM32MP_DDR_MAX_SIZE,
MT_MEMORY | MT_RW | MT_NS);
/* Prevent corruption of preloaded Device Tree */
mmap_add_region(DTB_BASE, DTB_BASE,
DTB_LIMIT - DTB_BASE,
MT_MEMORY | MT_RO | MT_SECURE);
MT_RO_DATA | MT_SECURE);
configure_mmu();
@ -351,8 +353,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
assert(paged_mem_params != NULL);
paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
(dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
STM32MP_DDR_SHMEM_SIZE);
stm32mp_get_ddr_ns_size();
paged_mem_params->image_info.image_max_size =
STM32MP_DDR_S_SIZE;

3
plat/st/stm32mp1/include/stm32mp1_private.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -21,4 +21,5 @@ void stm32mp1_syscfg_init(void);
void stm32mp1_syscfg_enable_io_compensation(void);
void stm32mp1_syscfg_disable_io_compensation(void);
uint32_t stm32mp_get_ddr_ns_size(void);
#endif /* STM32MP1_PRIVATE_H */

11
plat/st/stm32mp1/plat_image_load.c
View File

@ -1,9 +1,11 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <common/desc_image_load.h>
#include <plat/common/platform.h>
@ -21,6 +23,13 @@ void plat_flush_next_bl_params(void)
******************************************************************************/
bl_load_info_t *plat_get_bl_image_load_info(void)
{
bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID);
uint32_t ddr_ns_size = stm32mp_get_ddr_ns_size();
/* Max size is non-secure DDR end address minus image_base */
bl33->image_info.image_max_size = STM32MP_DDR_BASE + ddr_ns_size -
bl33->image_info.image_base;
return get_bl_load_info_from_mem_params_desc();
}

7
plat/st/stm32mp1/platform.mk
View File

@ -11,6 +11,11 @@ USE_COHERENT_MEM := 0
STM32_TF_VERSION ?= 0
# Enable dynamic memory mapping
PLAT_XLAT_TABLES_DYNAMIC := 1
$(eval $(call assert_boolean,PLAT_XLAT_TABLES_DYNAMIC))
$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
# Not needed for Cortex-A7
WORKAROUND_CVE_2017_5715:= 0
@ -152,8 +157,6 @@ STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed
STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
STM32_TF_LINKERFILE := ${BUILD_PLAT}/stm32mp1.ld
BL2_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
# Variables for use with stm32image
STM32IMAGEPATH ?= tools/stm32image
STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT}

5
plat/st/stm32mp1/stm32mp1_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -62,6 +62,9 @@
#ifdef AARCH32_SP_OPTEE
#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
#else
#define STM32MP_DDR_S_SIZE U(0)
#define STM32MP_DDR_SHMEM_SIZE U(0)
#endif
/* DDR power initializations */

23
plat/st/stm32mp1/stm32mp1_private.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -365,3 +365,24 @@ uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
return BSEC_OK;
}
#endif
/* Get the non-secure DDR size */
uint32_t stm32mp_get_ddr_ns_size(void)
{
static uint32_t ddr_ns_size;
uint32_t ddr_size;
if (ddr_ns_size != 0U) {
return ddr_ns_size;
}
ddr_size = dt_get_ddr_size();
if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) ||
(ddr_size > STM32MP_DDR_MAX_SIZE)) {
panic();
}
ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE);
return ddr_ns_size;
}

27
plat/st/stm32mp1/stm32mp1_security.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -35,29 +35,30 @@ static void init_tzc400(void)
{
unsigned long long region_base, region_top;
unsigned long long ddr_base = STM32MP_DDR_BASE;
unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
unsigned long long ddr_top = ddr_base + (ddr_size - 1U);
unsigned long long ddr_ns_size =
(unsigned long long)stm32mp_get_ddr_ns_size();
unsigned long long ddr_ns_top = ddr_base + (ddr_ns_size - 1U);
tzc400_init(STM32MP1_TZC_BASE);
tzc400_disable_filters();
#ifdef AARCH32_SP_OPTEE
/*
* Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the
* same configuration to all filters in the TZC.
*/
region_base = ddr_base;
region_top = ddr_top - STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE;
region_top = ddr_ns_top;
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
region_base,
region_top,
TZC_REGION_S_NONE,
TZC_REGION_NSEC_ALL_ACCESS_RDWR);
#ifdef AARCH32_SP_OPTEE
/* Region 2 set to cover all secure DRAM. */
region_base = region_top + 1U;
region_top = ddr_top - STM32MP_DDR_SHMEM_SIZE;
region_top += STM32MP_DDR_S_SIZE;
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 2,
region_base,
region_top,
@ -66,24 +67,12 @@ static void init_tzc400(void)
/* Region 3 set to cover non-secure shared memory DRAM. */
region_base = region_top + 1U;
region_top = ddr_top;
region_top += STM32MP_DDR_SHMEM_SIZE;
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 3,
region_base,
region_top,
TZC_REGION_S_NONE,
TZC_REGION_NSEC_ALL_ACCESS_RDWR);
#else
/*
* Region 1 set to cover all DRAM at 0xC000_0000. Apply the
* same configuration to all filters in the TZC.
*/
region_base = ddr_base;
region_top = ddr_top;
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
region_base,
region_top,
TZC_REGION_S_NONE,
TZC_REGION_NSEC_ALL_ACCESS_RDWR);
#endif
/* Raise an exception if a NS device tries to access secure memory */