rockchip: enable A53's erratum 855873 for rk3399
For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't support WriteEvict. and you will hit the condition L2ACTLR[3] with 0, as the Evict transactions should propagate to CCI-500 since it has snoop filters. Maybe this erratum applies to all Cortex-A53 cores so far, especially if RK3399's A53 is a r0p4. we should enable it to avoid data corruption, Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f Signed-off-by: Caesar Wang <wxt@rock-chips.com>
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@ -65,6 +65,9 @@ ENABLE_PLAT_COMPAT := 0
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$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
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# Enable workarounds for selected Cortex-A53 erratas.
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ERRATA_A53_855873 := 1
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# M0 source build
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PLAT_M0 := ${PLAT}m0
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BUILD_M0 := ${BUILD_PLAT}/m0
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