andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Tegra186: move platform specific MCE defines to tegra_def.h 

This patch moves the MCE's configurable parameters to tegra_def.h for
the Tegra186 SoC, to allow forward compatiblity.

Change-Id: If8660c1c09908a4064dbb67d5ca4fb78389cab13
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2016-12-12 14:24:17 -08:00
parent d81938ab3a
commit dec349c87d
2 changed files with 30 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
plat/nvidia/tegra/include/t186/tegra_def.h
View File

@ -31,6 +31,36 @@
#ifndef __TEGRA_DEF_H__
#define __TEGRA_DEF_H__
/*******************************************************************************
* MCE apertures used by the ARI interface
*
* Aperture 0 - Cpu0 (ARM Cortex A-57)
* Aperture 1 - Cpu1 (ARM Cortex A-57)
* Aperture 2 - Cpu2 (ARM Cortex A-57)
* Aperture 3 - Cpu3 (ARM Cortex A-57)
* Aperture 4 - Cpu4 (Denver15)
* Aperture 5 - Cpu5 (Denver15)
******************************************************************************/
#define MCE_ARI_APERTURE_0_OFFSET 0x0
#define MCE_ARI_APERTURE_1_OFFSET 0x10000
#define MCE_ARI_APERTURE_2_OFFSET 0x20000
#define MCE_ARI_APERTURE_3_OFFSET 0x30000
#define MCE_ARI_APERTURE_4_OFFSET 0x40000
#define MCE_ARI_APERTURE_5_OFFSET 0x50000
#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
/* number of apertures */
#define MCE_ARI_APERTURES_MAX 6
/* each ARI aperture is 64KB */
#define MCE_ARI_APERTURE_SIZE 0x10000
/*******************************************************************************
* CPU core id macros for the MCE_ONLINE_CORE ARI
******************************************************************************/
#define MCE_CORE_ID_MAX 8
#define MCE_CORE_ID_MASK 0x7
/*******************************************************************************
* These values are used by the PSCI implementation during the `CPU_SUSPEND`
* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'

40
plat/nvidia/tegra/soc/t186/drivers/include/mce.h
View File

@ -34,46 +34,6 @@
#include <mmio.h>
#include <tegra_def.h>
/*******************************************************************************
* MCE apertures used by the ARI interface
*
* Aperture 0 - Cpu0 (ARM Cortex A-57)
* Aperture 1 - Cpu1 (ARM Cortex A-57)
* Aperture 2 - Cpu2 (ARM Cortex A-57)
* Aperture 3 - Cpu3 (ARM Cortex A-57)
* Aperture 4 - Cpu4 (Denver15)
* Aperture 5 - Cpu5 (Denver15)
******************************************************************************/
#define MCE_ARI_APERTURE_0_OFFSET 0x0
#define MCE_ARI_APERTURE_1_OFFSET 0x10000
#define MCE_ARI_APERTURE_2_OFFSET 0x20000
#define MCE_ARI_APERTURE_3_OFFSET 0x30000
#define MCE_ARI_APERTURE_4_OFFSET 0x40000
#define MCE_ARI_APERTURE_5_OFFSET 0x50000
#define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET
/* number of apertures */
#define MCE_ARI_APERTURES_MAX 6
/* each ARI aperture is 64KB */
#define MCE_ARI_APERTURE_SIZE 0x10000
/*******************************************************************************
* CPU core ids - used by the MCE_ONLINE_CORE ARI
******************************************************************************/
typedef enum mce_core_id {
MCE_CORE_ID_DENVER_15_0,
MCE_CORE_ID_DENVER_15_1,
/* 2 and 3 are reserved */
MCE_CORE_ID_A57_0 = 4,
MCE_CORE_ID_A57_1,
MCE_CORE_ID_A57_2,
MCE_CORE_ID_A57_3,
MCE_CORE_ID_MAX
} mce_core_id_t;
#define MCE_CORE_ID_MASK 0x7
/*******************************************************************************
* MCE commands
******************************************************************************/