Merge "uniphier: fix typo and coding style" into integration
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commit
df42c3117b
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@ -35,7 +35,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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{
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{
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void *from_bl2;
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void *from_bl2;
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from_bl2 = (void *) arg0;
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from_bl2 = (void *)arg0;
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bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
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bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
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@ -76,7 +76,7 @@ void bl31_platform_setup(void)
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/* Enable and initialize the System level generic timer */
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/* Enable and initialize the System level generic timer */
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mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
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mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
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CNTCR_FCREQ(0U) | CNTCR_EN);
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CNTCR_FCREQ(0U) | CNTCR_EN);
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}
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}
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void bl31_plat_arch_setup(void)
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void bl31_plat_arch_setup(void)
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -21,34 +21,34 @@ static const interrupt_prop_t uniphier_interrupt_props[] = {
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/* SGI0 */
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/* SGI0 */
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INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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INTR_PROP_DESC(8, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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GIC_INTR_CFG_EDGE),
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/* SGI6 */
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/* SGI6 */
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INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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INTR_PROP_DESC(14, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
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GIC_INTR_CFG_EDGE),
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GIC_INTR_CFG_EDGE),
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/* G1S interrupts */
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/* G1S interrupts */
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/* Timer */
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/* Timer */
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INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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INTR_PROP_DESC(29, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_LEVEL),
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GIC_INTR_CFG_LEVEL),
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/* SGI1 */
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/* SGI1 */
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INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE),
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GIC_INTR_CFG_EDGE),
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/* SGI2 */
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/* SGI2 */
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INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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INTR_PROP_DESC(10, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE),
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GIC_INTR_CFG_EDGE),
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/* SGI3 */
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/* SGI3 */
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INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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INTR_PROP_DESC(11, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE),
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GIC_INTR_CFG_EDGE),
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/* SGI4 */
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/* SGI4 */
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INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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INTR_PROP_DESC(12, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE),
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GIC_INTR_CFG_EDGE),
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/* SGI5 */
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/* SGI5 */
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INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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INTR_PROP_DESC(13, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE),
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GIC_INTR_CFG_EDGE),
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/* SGI7 */
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/* SGI7 */
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INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP1S,
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GIC_INTR_CFG_EDGE)
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GIC_INTR_CFG_EDGE)
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};
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};
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static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr)
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static unsigned int uniphier_mpidr_to_core_pos(u_register_t mpidr)
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -331,7 +331,7 @@ int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
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assert(image_id < ARRAY_SIZE(uniphier_io_policies));
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assert(image_id < ARRAY_SIZE(uniphier_io_policies));
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*dev_handle = *(uniphier_io_policies[image_id].dev_handle);
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*dev_handle = *uniphier_io_policies[image_id].dev_handle;
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*image_spec = uniphier_io_policies[image_id].image_spec;
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*image_spec = uniphier_io_policies[image_id].image_spec;
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init_params = uniphier_io_policies[image_id].init_params;
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init_params = uniphier_io_policies[image_id].init_params;
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -14,9 +14,9 @@
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#define UNIPHIER_ROM_RSV0 0x59801200
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#define UNIPHIER_ROM_RSV0 0x59801200
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#define UNIPHIER_SLFRSTSEL 0x61843010
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#define UNIPHIER_SLFRSTSEL 0x61843010
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#define UNIPHIER_SLFRSTSEL_MASK (0x3 << 0)
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#define UNIPHIER_SLFRSTSEL_MASK GENMASK(1, 0)
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#define UNIPHIER_SLFRSTCTL 0x61843014
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#define UNIPHIER_SLFRSTCTL 0x61843014
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#define UNIPHIER_SLFRSTCTL_RST (1 << 0)
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#define UNIPHIER_SLFRSTCTL_RST BIT(0)
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#define MPIDR_AFFINITY_INVALID ((u_register_t)-1)
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#define MPIDR_AFFINITY_INVALID ((u_register_t)-1)
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@ -58,7 +58,7 @@ static void __dead2 uniphier_psci_pwr_domain_pwr_down_wfi(
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const psci_power_state_t *target_state)
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const psci_power_state_t *target_state)
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{
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{
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/*
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/*
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* The Boot ROM cannot distinguish warn and cold resets.
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* The Boot ROM cannot distinguish warm and cold resets.
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* Instead of the CPU reset, fake it.
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* Instead of the CPU reset, fake it.
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*/
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*/
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uniphier_holding_pen_release = MPIDR_AFFINITY_INVALID;
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uniphier_holding_pen_release = MPIDR_AFFINITY_INVALID;
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