From c84b6cb1aa9aed07899f15dd736fde48b6b20961 Mon Sep 17 00:00:00 2001 From: Joel Hutton Date: Fri, 4 May 2018 15:09:47 +0100 Subject: [PATCH 1/2] Add initial CPU support for Cortex-Deimos Change-Id: I2c4b06423fcd96af9351b88a5e2818059f981f1b Signed-off-by: Joel Hutton Signed-off-by: Dimitris Papastamos --- include/lib/cpus/aarch64/cortex_deimos.h | 23 +++++++++++ lib/cpus/aarch64/cortex_deimos.S | 51 ++++++++++++++++++++++++ plat/arm/board/fvp/platform.mk | 3 +- 3 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 include/lib/cpus/aarch64/cortex_deimos.h create mode 100644 lib/cpus/aarch64/cortex_deimos.S diff --git a/include/lib/cpus/aarch64/cortex_deimos.h b/include/lib/cpus/aarch64/cortex_deimos.h new file mode 100644 index 000000000..3c3656740 --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_deimos.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_DEIMOS_H__ +#define __CORTEX_DEIMOS_H__ + +#define CORTEX_DEIMOS_MIDR U(0x410FD0D0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_DEIMOS_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ +#define CORTEX_DEIMOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* __CORTEX_DEIMOS_H__ */ diff --git a/lib/cpus/aarch64/cortex_deimos.S b/lib/cpus/aarch64/cortex_deimos.S new file mode 100644 index 000000000..aec62a287 --- /dev/null +++ b/lib/cpus/aarch64/cortex_deimos.S @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * HW will do the cache maintenance while powering down + * --------------------------------------------- + */ +func cortex_deimos_core_pwr_dwn + /* --------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------- + */ + mrs x0, CORTEX_DEIMOS_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_DEIMOS_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_deimos_core_pwr_dwn + + /* --------------------------------------------- + * This function provides Cortex-Deimos specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_deimos_regs, "aS" +cortex_deimos_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_deimos_cpu_reg_dump + adr x6, cortex_deimos_regs + mrs x8, CORTEX_DEIMOS_CPUECTLR_EL1 + ret +endfunc cortex_deimos_cpu_reg_dump + +declare_cpu_ops cortex_deimos, CORTEX_DEIMOS_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_deimos_core_pwr_dwn diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index ed41d4cb8..2b1e0ac70 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -116,7 +116,8 @@ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ lib/cpus/aarch64/cortex_a73.S \ lib/cpus/aarch64/cortex_a75.S \ lib/cpus/aarch64/cortex_a76.S \ - lib/cpus/aarch64/cortex_ares.S + lib/cpus/aarch64/cortex_ares.S \ + lib/cpus/aarch64/cortex_deimos.S else FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S endif From 46e88703852958f9a212080724f2c6fdfb21fa1c Mon Sep 17 00:00:00 2001 From: Joel Hutton Date: Wed, 10 Jan 2018 16:06:07 +0000 Subject: [PATCH 2/2] Add initial CPU support for Cortex-Helios Change-Id: Ic0486131c493632eadf329f80b0b5904aed5e4ef Signed-off-by: Joel Hutton Signed-off-by: Dimitris Papastamos --- include/lib/cpus/aarch64/cortex_helios.h | 29 ++++++++++++++++++++ lib/cpus/aarch64/cortex_helios.S | 34 ++++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 include/lib/cpus/aarch64/cortex_helios.h create mode 100644 lib/cpus/aarch64/cortex_helios.S diff --git a/include/lib/cpus/aarch64/cortex_helios.h b/include/lib/cpus/aarch64/cortex_helios.h new file mode 100644 index 000000000..1098a124e --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_helios.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CORTEX_HELIOS_H__ +#define __CORTEX_HELIOS_H__ + +#define CORTEX_HELIOS_MIDR U(0x410FD060) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_HELIOS_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CORTEX_HELIOS_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ + +#define CORTEX_HELIOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* __CORTEX_HELIOS_H__ */ diff --git a/lib/cpus/aarch64/cortex_helios.S b/lib/cpus/aarch64/cortex_helios.S new file mode 100644 index 000000000..bcda74114 --- /dev/null +++ b/lib/cpus/aarch64/cortex_helios.S @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include +#include +#include +#include + +func cortex_helios_cpu_pwr_dwn + mrs x0, CORTEX_HELIOS_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HELIOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_HELIOS_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_helios_cpu_pwr_dwn + +.section .rodata.cortex_helios_regs, "aS" +cortex_helios_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_helios_cpu_reg_dump + adr x6, cortex_helios_regs + mrs x8, CORTEX_HELIOS_ECTLR_EL1 + ret +endfunc cortex_helios_cpu_reg_dump + +declare_cpu_ops cortex_helios, CORTEX_HELIOS_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_helios_cpu_pwr_dwn