From dfa6c540713ba546da65fe179ec1ef0fc1b1f7f5 Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Mon, 12 Apr 2021 12:49:54 +0100 Subject: [PATCH] Plat FVP: Fix Generic Timer interrupt types The Arm Generic Timer specification mandates that the interrupt associated with each timer is low level triggered, see: Arm Cortex-A76 Core: "Each timer provides an active-LOW interrupt output to the SoC." Arm Cortex-A53 MPCore Processor: "It generates timer events as active-LOW interrupt outputs and event streams." The following files in fdts\ fvp-base-gicv3-psci-common.dtsi fvp-base-gicv3-psci-aarch32-common.dtsi fvp-base-gicv2-psci-aarch32.dts fvp-base-gicv2-psci.dts fvp-foundation-gicv2-psci.dts fvp-foundation-gicv3-psci.dts describe interrupt types as edge rising IRQ_TYPE_EDGE_RISING = 0x01: interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; , see include\dt-bindings\interrupt-controller\arm-gic.h: which causes Linux to generate the warnings below: arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low arch_timer: WARNING: Please fix your firmware This patch adds GIC_CPU_MASK_RAW macro definition to include\dt-bindings\interrupt-controller\arm-gic.h, modifies interrupt type to IRQ_TYPE_LEVEL_LOW and makes use of type definitions in arm-gic.h. Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9 Signed-off-by: Alexei Fedorov --- fdts/fvp-base-gicv2-psci-aarch32.dts | 15 ++++++++++----- fdts/fvp-base-gicv2-psci.dts | 15 ++++++++++----- fdts/fvp-base-gicv3-psci-aarch32-common.dtsi | 16 +++++++++++----- fdts/fvp-base-gicv3-psci-common.dtsi | 15 ++++++++++----- fdts/fvp-foundation-gicv2-psci.dts | 15 ++++++++++----- fdts/fvp-foundation-gicv3-psci.dts | 15 ++++++++++----- .../dt-bindings/interrupt-controller/arm-gic.h | 5 +++++ 7 files changed, 66 insertions(+), 30 deletions(-) diff --git a/fdts/fvp-base-gicv2-psci-aarch32.dts b/fdts/fvp-base-gicv2-psci-aarch32.dts index 591ec5896..957aea511 100644 --- a/fdts/fvp-base-gicv2-psci-aarch32.dts +++ b/fdts/fvp-base-gicv2-psci-aarch32.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,7 @@ #define REG_32 #include "fvp-defs.dtsi" +#include /memreserve/ 0x80000000 0x00010000; @@ -100,10 +101,14 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff01>, - <1 14 0xff01>, - <1 11 0xff01>, - <1 10 0xff01>; + interrupts = , + , + , + ; clock-frequency = <100000000>; }; diff --git a/fdts/fvp-base-gicv2-psci.dts b/fdts/fvp-base-gicv2-psci.dts index 4b3942e19..f0c71b4a5 100644 --- a/fdts/fvp-base-gicv2-psci.dts +++ b/fdts/fvp-base-gicv2-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,6 +11,7 @@ #define AFF #include "fvp-defs.dtsi" +#include /memreserve/ 0x80000000 0x00010000; @@ -99,10 +100,14 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff01>, - <1 14 0xff01>, - <1 11 0xff01>, - <1 10 0xff01>; + interrupts = , + , + , + ; clock-frequency = <100000000>; }; diff --git a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi index 1a1bd12d2..85988e90f 100644 --- a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi +++ b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi @@ -1,9 +1,11 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include + /memreserve/ 0x80000000 0x00010000; / { @@ -100,10 +102,14 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff01>, - <1 14 0xff01>, - <1 11 0xff01>, - <1 10 0xff01>; + interrupts = , + , + , + ; clock-frequency = <100000000>; }; diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi index 192f5748a..0ef92733d 100644 --- a/fdts/fvp-base-gicv3-psci-common.dtsi +++ b/fdts/fvp-base-gicv3-psci-common.dtsi @@ -1,10 +1,11 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include +#include #define LEVEL 0 #define EDGE 2 @@ -161,10 +162,14 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff01>, - <1 14 0xff01>, - <1 11 0xff01>, - <1 10 0xff01>; + interrupts = , + , + , + ; clock-frequency = <100000000>; }; diff --git a/fdts/fvp-foundation-gicv2-psci.dts b/fdts/fvp-foundation-gicv2-psci.dts index 95a800e66..7dd9afdb8 100644 --- a/fdts/fvp-foundation-gicv2-psci.dts +++ b/fdts/fvp-foundation-gicv2-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,7 @@ #define CLUSTER_COUNT 1 #include "fvp-defs.dtsi" +#include /memreserve/ 0x80000000 0x00010000; @@ -100,10 +101,14 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff01>, - <1 14 0xff01>, - <1 11 0xff01>, - <1 10 0xff01>; + interrupts = , + , + , + ; clock-frequency = <100000000>; }; diff --git a/fdts/fvp-foundation-gicv3-psci.dts b/fdts/fvp-foundation-gicv3-psci.dts index c295dc1c8..0b265ad5e 100644 --- a/fdts/fvp-foundation-gicv3-psci.dts +++ b/fdts/fvp-foundation-gicv3-psci.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,6 +12,7 @@ #define CLUSTER_COUNT 1 #include "fvp-defs.dtsi" +#include /memreserve/ 0x80000000 0x00010000; @@ -109,10 +110,14 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff01>, - <1 14 0xff01>, - <1 11 0xff01>, - <1 10 0xff01>; + interrupts = , + , + , + ; clock-frequency = <100000000>; }; diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h index aa9158cb1..024a6c602 100644 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ b/include/dt-bindings/interrupt-controller/arm-gic.h @@ -18,4 +18,9 @@ #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 +/* + * Interrupt specifier cell 2. + */ +#define GIC_CPU_MASK_RAW(x) ((x) << 8) + #endif