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Merge pull request #371 from vwadekar/retention-entry-v3 

Retention entry v3
This commit is contained in:
Achin Gupta 2015-08-25 22:49:04 +01:00
parent 468f808cb8 b42192bcbd
commit e04723e213
4 changed files with 73 additions and 2 deletions
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25
include/lib/cpus/aarch64/cortex_a53.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -34,6 +34,15 @@
/* Cortex-A53 midr for revision 0 */
#define CORTEX_A53_MIDR 0x410FD030
/* Retention timer tick definitions */
#define RETENTION_ENTRY_TICKS_2 0x1
#define RETENTION_ENTRY_TICKS_8 0x2
#define RETENTION_ENTRY_TICKS_32 0x3
#define RETENTION_ENTRY_TICKS_64 0x4
#define RETENTION_ENTRY_TICKS_128 0x5
#define RETENTION_ENTRY_TICKS_256 0x6
#define RETENTION_ENTRY_TICKS_512 0x7
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
@ -41,6 +50,12 @@
#define CPUECTLR_SMP_BIT (1 << 6)
#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
#define CPUECTLR_FPU_RET_CTRL_SHIFT 3
#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
@ -56,4 +71,12 @@
#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14)
#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3)
/*******************************************************************************
* L2 Extended Control register specific definitions.
******************************************************************************/
#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */
#define L2ECTLR_RET_CTRL_SHIFT 0
#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
#endif /* __CORTEX_A53_H__ */

22
include/lib/cpus/aarch64/cortex_a57.h
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -34,6 +34,15 @@
/* Cortex-A57 midr for revision 0 */
#define CORTEX_A57_MIDR 0x410FD070
/* Retention timer tick definitions */
#define RETENTION_ENTRY_TICKS_2 0x1
#define RETENTION_ENTRY_TICKS_8 0x2
#define RETENTION_ENTRY_TICKS_32 0x3
#define RETENTION_ENTRY_TICKS_64 0x4
#define RETENTION_ENTRY_TICKS_128 0x5
#define RETENTION_ENTRY_TICKS_256 0x6
#define RETENTION_ENTRY_TICKS_512 0x7
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
@ -44,6 +53,9 @@
#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
@ -63,4 +75,12 @@
#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Extended Control register specific definitions.
******************************************************************************/
#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */
#define L2ECTLR_RET_CTRL_SHIFT 0
#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
#endif /* __CORTEX_A57_H__ */

22
plat/nvidia/tegra/common/aarch64/tegra_helpers.S
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@ -57,6 +57,28 @@
*/
.macro cpu_init_common
#if ENABLE_L2_DYNAMIC_RETENTION
/* ---------------------------
* Enable processor retention
* ---------------------------
*/
mrs x0, L2ECTLR_EL1
mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT
bic x0, x0, #L2ECTLR_RET_CTRL_MASK
orr x0, x0, x1
msr L2ECTLR_EL1, x0
isb
#endif
#if ENABLE_CPU_DYNAMIC_RETENTION
mrs x0, CPUECTLR_EL1
mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT
bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK
orr x0, x0, x1
msr CPUECTLR_EL1, x0
isb
#endif
#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS
/* -------------------------------------------------------
* Enable L2 and CPU ECTLR RW access from non-secure world

6
plat/nvidia/tegra/soc/t210/platform_t210.mk
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@ -40,6 +40,12 @@ $(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1
$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS))
ENABLE_L2_DYNAMIC_RETENTION := 1
$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION))
ENABLE_CPU_DYNAMIC_RETENTION := 1
$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION))
PLATFORM_CLUSTER_COUNT := 2
$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))