Merge pull request #1605 from sivadur/integration
Add support new Xilinx Versal ACAP platform
This commit is contained in:
Antonio Niño Díaz
GitHub
commit
e07666de14
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Trusted Firmware-A for Xilinx Versal
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================================
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Trusted Firmware-A implements the EL3 firmware layer for Xilinx Versal.
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The platform only uses the runtime part of TF-A as Xilinx Versal already has a
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BootROM (BL1) and PMC FW (BL2).
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BL31 is TF-A.
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BL32 is an optional Secure Payload.
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BL33 is the non-secure world software (U-Boot, Linux etc).
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To build:
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```bash
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make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31
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```
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To build ATF for different platform (for now its just versal virtual "versal_virt")
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```bash
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make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal VERSAL_PLATFORM=versal_virt bl31
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```
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# Xilinx Versal platform specific build options
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* `VERSAL_ATF_MEM_BASE`: Specifies the base address of the bl31 binary.
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* `VERSAL_ATF_MEM_SIZE`: Specifies the size of the memory region of the bl31 binary.
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* `VERSAL_BL32_MEM_BASE`: Specifies the base address of the bl32 binary.
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* `VERSAL_BL32_MEM_SIZE`: Specifies the size of the memory region of the bl32 binary.
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* `VERSAL_CONSOLE`: Select the console driver. Options:
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- `pl011`, `pl011_0`: ARM pl011 UART 0
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- `pl011_1` : ARM pl011 UART 1
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* `VERSAL_PLATFORM`: Select the platform. Options:
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- `versal_virt` : Versal Virtual platform
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@ -0,0 +1,75 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <generic_delay_timer.h>
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#include <mmio.h>
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#include <platform.h>
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#include <xlat_tables.h>
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#include "../versal_def.h"
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#include "../versal_private.h"
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/*
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* Table of regions to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t plat_versal_mmap[] = {
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MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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{ 0 }
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};
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const mmap_region_t *plat_versal_get_mmap(void)
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{
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return plat_versal_mmap;
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}
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static void versal_print_platform_name(void)
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{
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NOTICE("ATF running on Xilinx %s\n", PLATFORM_NAME);
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}
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void versal_config_setup(void)
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{
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uint32_t val;
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versal_print_platform_name();
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mmio_write_32(VERSAL_CRL_IOU_SWITCH_CTRL,
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VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT |
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(0x20 << VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT));
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/* Global timer init - Program time stamp reference clk */
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val = mmio_read_32(VERSAL_CRL_TIMESTAMP_REF_CTRL);
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val |= VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
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mmio_write_32(VERSAL_CRL_TIMESTAMP_REF_CTRL, val);
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/* Clear reset of timestamp reg */
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mmio_write_32(VERSAL_CRL_RST_TIMESTAMP_OFFSET, 0x0);
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/* Program freq register in System counter and enable system counter. */
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mmio_write_32(VERSAL_IOU_SCNTRS_BASE_FREQ, VERSAL_CPU_CLOCK);
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mmio_write_32(VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG,
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VERSAL_IOU_SCNTRS_CONTROL_EN);
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generic_delay_timer_init();
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return VERSAL_CPU_CLOCK;
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}
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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#ifdef PRELOADED_BL33_BASE
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return PRELOADED_BL33_BASE;
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#else
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return PLAT_VERSAL_NS_IMAGE_OFFSET;
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#endif
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}
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@ -0,0 +1,73 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <gicv3.h>
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#include <platform_def.h>
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.globl plat_secondary_cold_boot_setup
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.globl plat_is_my_cpu_primary
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.globl versal_calc_core_pos
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.globl platform_mem_init
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.globl plat_my_core_pos
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* TODO: Should we read the PSYS register to make sure
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* that the request has gone through.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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mrs x0, mpidr_el1
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/*
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* There is no sane reason to come out of this wfi. This
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* cpu will be powered on and reset by the cpu_on pm api
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*/
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dsb sy
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bl plat_panic_handler
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endfunc plat_secondary_cold_boot_setup
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func plat_is_my_cpu_primary
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mov x9, x30
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bl plat_my_core_pos
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cmp x0, #VERSAL_PRIMARY_CPU
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cset x0, eq
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ret x9
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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* This function uses the versal_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b versal_calc_core_pos
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endfunc plat_my_core_pos
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func versal_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc versal_calc_core_pos
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/* ---------------------------------------------------------------------
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* We don't need to carry out any memory initialization on VERSAL
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* platform. The Secure RAM is accessible straight away.
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* ---------------------------------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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@ -0,0 +1,120 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <bl_common.h>
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#include <bl31.h>
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#include <console.h>
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#include <debug.h>
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#include <errno.h>
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#include <platform.h>
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#include <pl011.h>
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#include <xlat_tables.h>
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#include "versal_private.h"
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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static console_pl011_t versal_runtime_console;
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/*
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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*/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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assert(sec_state_is_valid(type));
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if (type == NON_SECURE)
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return &bl33_image_ep_info;
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return &bl32_image_ep_info;
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}
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/*
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* Perform any BL31 specific platform actions. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
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* are lost (potentially). This needs to be done before the MMU is initialized
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* so that the memory layout can be used while creating page tables.
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*/
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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/* Initialize the console to provide early debug support */
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int rc = console_pl011_register(VERSAL_UART_BASE,
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VERSAL_UART_CLOCK,
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VERSAL_UART_BAUDRATE,
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&versal_runtime_console);
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if (rc == 0)
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panic();
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console_set_scope(&versal_runtime_console.console, CONSOLE_FLAG_BOOT |
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CONSOLE_FLAG_RUNTIME);
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/* Initialize the platform config for future decision making */
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versal_config_setup();
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/* There are no parameters from BL2 if BL31 is a reset vector */
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assert(arg0 == 0U);
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assert(arg1 == 0U);
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/*
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* Do initial security configuration to allow DRAM/device access. On
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* Base VERSAL only DRAM security is programmable (via TrustZone), but
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* other platforms might have more programmable security devices
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* present.
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*/
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/* Populate common information for BL32 and BL33 */
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SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
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SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
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SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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/* use build time defaults in JTAG boot mode */
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = 0;
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
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NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
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}
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void bl31_platform_setup(void)
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{
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/* Initialize the gic cpu and distributor interfaces */
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plat_versal_gic_driver_init();
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plat_versal_gic_init();
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}
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void bl31_plat_runtime_setup(void)
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{
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}
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/*
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* Perform the very early platform specific architectural setup here.
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*/
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void bl31_plat_arch_setup(void)
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{
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const mmap_region_t bl_regions[] = {
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MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
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MT_MEMORY | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE),
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MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
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MT_RO_DATA | MT_SECURE),
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MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
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MT_DEVICE | MT_RW | MT_SECURE),
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{0}
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};
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setup_page_tables(bl_regions, plat_versal_get_mmap());
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enable_mmu_el3(0);
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}
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@ -0,0 +1,109 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_MACROS_S
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#define PLAT_MACROS_S
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#include "../include/platform_def.h"
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#include <gic_common.h>
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#include <gicv2.h>
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#include <gicv3.h>
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.section .rodata.gic_reg_name, "aS"
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/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
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gicc_regs:
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.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
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/* Applicable only to GICv3 with SRE enabled */
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icc_regs:
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.asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
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/* Registers common to both GICv2 and GICv3 */
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t0x"
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/* ---------------------------------------------
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* The below utility macro prints out relevant GIC
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* registers whenever an unhandled exception is
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* taken in BL31 on Versal platform.
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* Expects: GICD base in x16, GICC base in x17
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* Clobbers: x0 - x10, sp
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* ---------------------------------------------
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*/
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.macro versal_print_gic_regs
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/* Check for GICv3 system register access */
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mrs x7, id_aa64pfr0_el1
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ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
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cmp x7, #1
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b.ne print_gicv2
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/* Check for SRE enable */
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mrs x8, ICC_SRE_EL3
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tst x8, #ICC_SRE_SRE_BIT
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b.eq print_gicv2
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/* Load the icc reg list to x6 */
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adr x6, icc_regs
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/* Load the icc regs to gp regs used by str_in_crash_buf_print */
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mrs x8, ICC_HPPIR0_EL1
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mrs x9, ICC_HPPIR1_EL1
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mrs x10, ICC_CTLR_EL3
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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b print_gic_common
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print_gicv2:
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/* Load the gicc reg list to x6 */
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adr x6, gicc_regs
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/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
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ldr w8, [x17, #GICC_HPPIR]
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ldr w9, [x17, #GICC_AHPPIR]
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ldr w10, [x17, #GICC_CTLR]
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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print_gic_common:
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/* Print the GICD_ISPENDR regs */
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add x7, x16, #GICD_ISPENDR
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adr x4, gicd_pend_reg
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bl asm_print_str
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gicd_ispendr_loop:
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sub x4, x7, x16
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cmp x4, #0x280
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b.eq exit_print_gic_regs
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bl asm_print_hex
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adr x4, spacer
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bl asm_print_str
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ldr x4, [x7], #8
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bl asm_print_hex
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adr x4, newline
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bl asm_print_str
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b gicd_ispendr_loop
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exit_print_gic_regs:
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.endm
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/* ---------------------------------------------
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* The below required platform porting macro
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* prints out relevant GIC and CCI registers
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* whenever an unhandled exception is taken in
|
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* BL31.
|
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* Clobbers: x0 - x10, x16, x17, sp
|
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* ---------------------------------------------
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*/
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.macro plat_crash_print_regs
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mov_imm x17, PLAT_VERSAL_GICD_BASE
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mov_imm x16, PLAT_VERSAL_GICR_BASE
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versal_print_gic_regs
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.endm
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#endif /* PLAT_MACROS_S */
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|
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@ -0,0 +1,101 @@
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/*
|
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
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|
||||
#include <arch.h>
|
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#include "../versal_def.h"
|
||||
|
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/*******************************************************************************
|
||||
* Generic platform constants
|
||||
******************************************************************************/
|
||||
|
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/* Size of cacheable stacks */
|
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#define PLATFORM_STACK_SIZE 0x440
|
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|
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#define PLATFORM_CORE_COUNT 2
|
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#define PLAT_MAX_PWR_LVL 1
|
||||
#define PLAT_MAX_RET_STATE 1
|
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#define PLAT_MAX_OFF_STATE 2
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|
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/*******************************************************************************
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* BL31 specific defines.
|
||||
******************************************************************************/
|
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/*
|
||||
* Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
|
||||
* present). BL31_BASE is calculated using the current BL31 debug size plus a
|
||||
* little space for growth.
|
||||
*/
|
||||
#ifndef VERSAL_ATF_MEM_BASE
|
||||
# define BL31_BASE 0xfffea000
|
||||
# define BL31_LIMIT 0xffffffff
|
||||
#else
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||||
# define BL31_BASE (VERSAL_ATF_MEM_BASE)
|
||||
# define BL31_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE - 1)
|
||||
# ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
|
||||
# define BL31_PROGBITS_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_PROGBITS_SIZE - 1)
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* BL32 specific defines.
|
||||
******************************************************************************/
|
||||
#ifndef VERSAL_BL32_MEM_BASE
|
||||
# define BL32_BASE 0x60000000
|
||||
# define BL32_LIMIT 0x7fffffff
|
||||
#else
|
||||
# define BL32_BASE (VERSAL_BL32_MEM_BASE)
|
||||
# define BL32_LIMIT (VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE - 1)
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* BL33 specific defines.
|
||||
******************************************************************************/
|
||||
#ifndef PRELOADED_BL33_BASE
|
||||
# define PLAT_VERSAL_NS_IMAGE_OFFSET 0x8000000
|
||||
#else
|
||||
# define PLAT_VERSAL_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* TSP specific defines.
|
||||
******************************************************************************/
|
||||
#define TSP_SEC_MEM_BASE BL32_BASE
|
||||
#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
|
||||
|
||||
/* ID of the secure physical generic timer interrupt used by the TSP */
|
||||
#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform specific page table and MMU setup constants
|
||||
******************************************************************************/
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
|
||||
#define MAX_MMAP_REGIONS 7
|
||||
#define MAX_XLAT_TABLES 5
|
||||
|
||||
#define CACHE_WRITEBACK_SHIFT 6
|
||||
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
#define PLAT_VERSAL_GICD_BASE 0xF9000000
|
||||
#define PLAT_VERSAL_GICR_BASE 0xF9080000
|
||||
|
||||
/*
|
||||
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
|
||||
* terminology. On a GICv2 system or mode, the lists will be merged and treated
|
||||
* as Group 0 interrupts.
|
||||
*/
|
||||
#define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER
|
||||
#define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER
|
||||
|
||||
#define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \
|
||||
INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
|
||||
GIC_INTR_CFG_LEVEL)
|
||||
|
||||
#define PLAT_VERSAL_G0_IRQ_PROPS(grp)
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <debug.h>
|
||||
#include <mmio.h>
|
||||
#include <platform.h>
|
||||
#include <psci.h>
|
||||
#include "versal_private.h"
|
||||
|
||||
static uintptr_t versal_sec_entry;
|
||||
|
||||
static int versal_nopmc_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
uint32_t r;
|
||||
unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
|
||||
|
||||
VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
|
||||
|
||||
if (cpu_id == -1)
|
||||
return PSCI_E_INTERN_FAIL;
|
||||
|
||||
/*
|
||||
* program RVBAR
|
||||
*/
|
||||
mmio_write_32(FPD_APU_RVBAR_L_0 + (cpu_id << 3), versal_sec_entry);
|
||||
mmio_write_32(FPD_APU_RVBAR_H_0 + (cpu_id << 3), versal_sec_entry >> 32);
|
||||
|
||||
/*
|
||||
* clear VINITHI
|
||||
*/
|
||||
r = mmio_read_32(FPD_APU_CONFIG_0);
|
||||
r &= ~(1 << FPD_APU_CONFIG_0_VINITHI_SHIFT << cpu_id);
|
||||
mmio_write_32(FPD_APU_CONFIG_0, r);
|
||||
|
||||
/*
|
||||
* FIXME: Add power up sequence, By default it works
|
||||
* now without the need of it as it was powered up by
|
||||
* default.
|
||||
*/
|
||||
|
||||
/*
|
||||
* clear power down request
|
||||
*/
|
||||
r = mmio_read_32(FPD_APU_PWRCTL);
|
||||
r &= ~(1 << cpu_id);
|
||||
mmio_write_32(FPD_APU_PWRCTL, r);
|
||||
|
||||
/*
|
||||
* release core reset
|
||||
*/
|
||||
r = mmio_read_32(CRF_RST_APU);
|
||||
r &= ~((CRF_RST_APU_ACPU_PWRON_RESET |
|
||||
CRF_RST_APU_ACPU_RESET) << cpu_id);
|
||||
mmio_write_32(CRF_RST_APU, r);
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
void versal_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
/* Enable the gic cpu interface */
|
||||
plat_versal_gic_pcpu_init();
|
||||
|
||||
/* Program the gic per-cpu distributor or re-distributor interface */
|
||||
plat_versal_gic_cpuif_enable();
|
||||
}
|
||||
|
||||
static const struct plat_psci_ops versal_nopmc_psci_ops = {
|
||||
.pwr_domain_on = versal_nopmc_pwr_domain_on,
|
||||
.pwr_domain_on_finish = versal_pwr_domain_on_finish,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Export the platform specific power ops.
|
||||
******************************************************************************/
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const struct plat_psci_ops **psci_ops)
|
||||
{
|
||||
versal_sec_entry = sec_entrypoint;
|
||||
|
||||
*psci_ops = &versal_nopmc_psci_ops;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <platform_def.h>
|
||||
|
||||
static const unsigned char plat_power_domain_tree_desc[] = {1, PLATFORM_CORE_COUNT};
|
||||
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return plat_power_domain_tree_desc;
|
||||
}
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include <platform.h>
|
||||
#include "versal_private.h"
|
||||
|
||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||
{
|
||||
if (mpidr & MPIDR_CLUSTER_MASK)
|
||||
return -1;
|
||||
|
||||
if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT)
|
||||
return -1;
|
||||
|
||||
return versal_calc_core_pos(mpidr);
|
||||
}
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
override PROGRAMMABLE_RESET_ADDRESS := 1
|
||||
PSCI_EXTENDED_STATE_ID := 1
|
||||
A53_DISABLE_NON_TEMPORAL_HINT := 0
|
||||
SEPARATE_CODE_AND_RODATA := 1
|
||||
override RESET_TO_BL31 := 1
|
||||
PL011_GENERIC_UART := 1
|
||||
MULTI_CONSOLE_API := 1
|
||||
|
||||
ifdef VERSAL_ATF_MEM_BASE
|
||||
$(eval $(call add_define,VERSAL_ATF_MEM_BASE))
|
||||
|
||||
ifndef VERSAL_ATF_MEM_SIZE
|
||||
$(error "VERSAL_ATF_BASE defined without VERSAL_ATF_SIZE")
|
||||
endif
|
||||
$(eval $(call add_define,VERSAL_ATF_MEM_SIZE))
|
||||
|
||||
ifdef VERSAL_ATF_MEM_PROGBITS_SIZE
|
||||
$(eval $(call add_define,VERSAL_ATF_MEM_PROGBITS_SIZE))
|
||||
endif
|
||||
endif
|
||||
|
||||
ifdef VERSAL_BL32_MEM_BASE
|
||||
$(eval $(call add_define,VERSAL_BL32_MEM_BASE))
|
||||
|
||||
ifndef VERSAL_BL32_MEM_SIZE
|
||||
$(error "VERSAL_BL32_BASE defined without VERSAL_BL32_SIZE")
|
||||
endif
|
||||
$(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
|
||||
endif
|
||||
|
||||
VERSAL_PLATFORM ?= versal_virt
|
||||
$(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM}))
|
||||
|
||||
VERSAL_CONSOLE ?= pl011
|
||||
$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
|
||||
|
||||
PLAT_INCLUDES := -Iplat/xilinx/versal/include/
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
|
||||
lib/xlat_tables/aarch64/xlat_tables.c \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/delay_timer/generic_delay_timer.c \
|
||||
drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v3/gicv3_main.c \
|
||||
drivers/arm/gic/v3/gicv3_helpers.c \
|
||||
drivers/arm/pl011/aarch64/pl011_console.S \
|
||||
plat/common/plat_gicv3.c \
|
||||
plat/xilinx/versal/aarch64/versal_helpers.S \
|
||||
plat/xilinx/versal/aarch64/versal_common.c
|
||||
|
||||
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
|
||||
lib/cpus/aarch64/cortex_a72.S \
|
||||
plat/common/plat_psci_common.c \
|
||||
plat/xilinx/versal/bl31_versal_setup.c \
|
||||
plat/xilinx/versal/plat_psci.c \
|
||||
plat/xilinx/versal/plat_versal.c \
|
||||
plat/xilinx/versal/plat_topology.c \
|
||||
plat/xilinx/versal/sip_svc_setup.c \
|
||||
plat/xilinx/versal/versal_gicv3.c
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/* Top level SMC handler for SiP calls. Dispatch PM calls to PM SMC handler. */
|
||||
|
||||
#include <debug.h>
|
||||
#include <runtime_svc.h>
|
||||
#include <uuid.h>
|
||||
|
||||
/* SMC function IDs for SiP Service queries */
|
||||
#define VERSAL_SIP_SVC_CALL_COUNT 0x8200ff00
|
||||
#define VERSAL_SIP_SVC_UID 0x8200ff01
|
||||
#define VERSAL_SIP_SVC_VERSION 0x8200ff03
|
||||
|
||||
/* SiP Service Calls version numbers */
|
||||
#define SIP_SVC_VERSION_MAJOR 0
|
||||
#define SIP_SVC_VERSION_MINOR 1
|
||||
|
||||
/* These macros are used to identify PM calls from the SMC function ID */
|
||||
#define PM_FID_MASK 0xf000u
|
||||
#define PM_FID_VALUE 0u
|
||||
#define is_pm_fid(_fid) (((_fid) & PM_FID_MASK) == PM_FID_VALUE)
|
||||
|
||||
/* SiP Service UUID */
|
||||
DEFINE_SVC_UUID2(versal_sip_uuid,
|
||||
0x2ab9e4ec, 0x93b9, 0x11e7, 0xa0, 0x19,
|
||||
0xdf, 0xe0, 0xdb, 0xad, 0x0a, 0xe0);
|
||||
|
||||
/**
|
||||
* sip_svc_setup() - Setup SiP Service
|
||||
*
|
||||
* Invokes PM setup
|
||||
*/
|
||||
static int32_t sip_svc_setup(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* sip_svc_smc_handler() - Top-level SiP Service SMC handler
|
||||
*
|
||||
* Handler for all SiP SMC calls. Handles standard SIP requests
|
||||
* and calls PM SMC handler if the call is for a PM-API function.
|
||||
*/
|
||||
uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
|
||||
u_register_t x1,
|
||||
u_register_t x2,
|
||||
u_register_t x3,
|
||||
u_register_t x4,
|
||||
void *cookie,
|
||||
void *handle,
|
||||
u_register_t flags)
|
||||
{
|
||||
/* Let PM SMC handler deal with PM-related requests */
|
||||
switch (smc_fid) {
|
||||
case VERSAL_SIP_SVC_CALL_COUNT:
|
||||
/* PM functions + default functions */
|
||||
SMC_RET1(handle, 2);
|
||||
|
||||
case VERSAL_SIP_SVC_UID:
|
||||
SMC_UUID_RET(handle, versal_sip_uuid);
|
||||
|
||||
case VERSAL_SIP_SVC_VERSION:
|
||||
SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR);
|
||||
|
||||
default:
|
||||
WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid);
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
}
|
||||
}
|
||||
|
||||
/* Register PM Service Calls as runtime service */
|
||||
DECLARE_RT_SVC(
|
||||
sip_svc,
|
||||
OEN_SIP_START,
|
||||
OEN_SIP_END,
|
||||
SMC_TYPE_FAST,
|
||||
sip_svc_setup,
|
||||
sip_svc_smc_handler);
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VERSAL_DEF_H
|
||||
#define VERSAL_DEF_H
|
||||
|
||||
#include <common_def.h>
|
||||
|
||||
/* List all consoles */
|
||||
#define VERSAL_CONSOLE_ID_pl011 1
|
||||
#define VERSAL_CONSOLE_ID_pl011_0 1
|
||||
#define VERSAL_CONSOLE_ID_pl011_1 2
|
||||
#define VERSAL_CONSOLE_ID_dcc 3
|
||||
|
||||
#define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE)
|
||||
|
||||
/* List all supported platforms */
|
||||
#define VERSAL_PLATFORM_ID_versal_virt 1
|
||||
|
||||
#define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM)
|
||||
|
||||
/* Firmware Image Package */
|
||||
#define VERSAL_PRIMARY_CPU 0
|
||||
|
||||
/*******************************************************************************
|
||||
* memory map related constants
|
||||
******************************************************************************/
|
||||
#define DEVICE0_BASE 0xFF000000
|
||||
#define DEVICE0_SIZE 0x00E00000
|
||||
#define DEVICE1_BASE 0xF9000000
|
||||
#define DEVICE1_SIZE 0x00800000
|
||||
|
||||
/* CRL */
|
||||
#define VERSAL_CRL 0xFF5E0000
|
||||
#define VERSAL_CRL_IOU_SWITCH_CTRL (VERSAL_CRL + 0x114)
|
||||
#define VERSAL_CRL_TIMESTAMP_REF_CTRL (VERSAL_CRL + 0x14C)
|
||||
#define VERSAL_CRL_RST_TIMESTAMP_OFFSET (VERSAL_CRL + 0x348)
|
||||
|
||||
#define VERSAL_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 25)
|
||||
#define VERSAL_IOU_SWITCH_CTRL_CLKACT_BIT (1 << 25)
|
||||
#define VERSAL_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
|
||||
|
||||
/* IOU SCNTRS */
|
||||
#define VERSAL_IOU_SCNTRS 0xFF140000
|
||||
#define VERSAL_IOU_SCNTRS_COUNTER_CONTROL_REG (VERSAL_IOU_SCNTRS + 0x0)
|
||||
#define VERSAL_IOU_SCNTRS_BASE_FREQ (VERSAL_IOU_SCNTRS + 0x20)
|
||||
|
||||
#define VERSAL_IOU_SCNTRS_CONTROL_EN 1
|
||||
|
||||
/*******************************************************************************
|
||||
* IRQ constants
|
||||
******************************************************************************/
|
||||
#define VERSAL_IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
/*******************************************************************************
|
||||
* UART related constants
|
||||
******************************************************************************/
|
||||
#define VERSAL_UART0_BASE 0xFF000000
|
||||
#define VERSAL_UART1_BASE 0xFF010000
|
||||
|
||||
#if VERSAL_CONSOLE_IS(pl011)
|
||||
# define VERSAL_UART_BASE VERSAL_UART0_BASE
|
||||
#elif VERSAL_CONSOLE_IS(pl011_1)
|
||||
# define VERSAL_UART_BASE VERSAL_UART1_BASE
|
||||
#else
|
||||
# error "invalid VERSAL_CONSOLE"
|
||||
#endif
|
||||
|
||||
#define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE
|
||||
#define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK
|
||||
#define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform related constants
|
||||
******************************************************************************/
|
||||
#if VERSAL_PLATFORM_IS(versal_virt)
|
||||
# define PLATFORM_NAME "Versal Virt"
|
||||
# define VERSAL_UART_CLOCK 25000000
|
||||
# define VERSAL_UART_BAUDRATE 115200
|
||||
# define VERSAL_CPU_CLOCK 62500000
|
||||
#endif
|
||||
|
||||
/* Access control register defines */
|
||||
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
|
||||
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
|
||||
|
||||
/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
|
||||
#define CRF_BASE 0xFD1A0000
|
||||
#define CRF_SIZE 0x00600000
|
||||
|
||||
/* CRF registers and bitfields */
|
||||
#define CRF_RST_APU (CRF_BASE + 0X00000300)
|
||||
|
||||
#define CRF_RST_APU_ACPU_RESET (1 << 0)
|
||||
#define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10)
|
||||
|
||||
/* APU registers and bitfields */
|
||||
#define FPD_APU_BASE 0xFD5C0000
|
||||
#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20)
|
||||
#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40)
|
||||
#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44)
|
||||
#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90)
|
||||
|
||||
#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8
|
||||
|
||||
#endif /* VERSAL_DEF_H */
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <gicv3.h>
|
||||
#include <interrupt_props.h>
|
||||
#include <platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <utils.h>
|
||||
#include "versal_private.h"
|
||||
|
||||
/******************************************************************************
|
||||
* The following functions are defined as weak to allow a platform to override
|
||||
* the way the GICv3 driver is initialised and used.
|
||||
*****************************************************************************/
|
||||
#pragma weak plat_versal_gic_driver_init
|
||||
#pragma weak plat_versal_gic_init
|
||||
#pragma weak plat_versal_gic_cpuif_enable
|
||||
#pragma weak plat_versal_gic_cpuif_disable
|
||||
#pragma weak plat_versal_gic_pcpu_init
|
||||
#pragma weak plat_versal_gic_redistif_on
|
||||
#pragma weak plat_versal_gic_redistif_off
|
||||
|
||||
/* The GICv3 driver only needs to be initialized in EL3 */
|
||||
static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
|
||||
|
||||
static const interrupt_prop_t versal_interrupt_props[] = {
|
||||
PLAT_VERSAL_G1S_IRQ_PROPS(INTR_GROUP1S),
|
||||
PLAT_VERSAL_G0_IRQ_PROPS(INTR_GROUP0)
|
||||
};
|
||||
|
||||
/*
|
||||
* We save and restore the GICv3 context on system suspend. Allocate the
|
||||
* data in the designated EL3 Secure carve-out memory.
|
||||
*/
|
||||
static gicv3_redist_ctx_t rdist_ctx __section("versal_el3_tzc_dram");
|
||||
static gicv3_dist_ctx_t dist_ctx __section("versal_el3_tzc_dram");
|
||||
|
||||
/*
|
||||
* MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
|
||||
* to core position.
|
||||
*
|
||||
* Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
|
||||
* values read from GICR_TYPER don't have an MT field. To reuse the same
|
||||
* translation used for CPUs, we insert MT bit read from the PE's MPIDR into
|
||||
* that read from GICR_TYPER.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
* - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
|
||||
* - No CPUs implemented in the system use affinity level 3.
|
||||
*/
|
||||
static unsigned int versal_gicv3_mpidr_hash(u_register_t mpidr)
|
||||
{
|
||||
mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
|
||||
return versal_calc_core_pos(mpidr);
|
||||
}
|
||||
|
||||
static const gicv3_driver_data_t versal_gic_data __unused = {
|
||||
.gicd_base = PLAT_VERSAL_GICD_BASE,
|
||||
.gicr_base = PLAT_VERSAL_GICR_BASE,
|
||||
.interrupt_props = versal_interrupt_props,
|
||||
.interrupt_props_num = ARRAY_SIZE(versal_interrupt_props),
|
||||
.rdistif_num = PLATFORM_CORE_COUNT,
|
||||
.rdistif_base_addrs = rdistif_base_addrs,
|
||||
.mpidr_to_core_pos = versal_gicv3_mpidr_hash
|
||||
};
|
||||
|
||||
void __init plat_versal_gic_driver_init(void)
|
||||
{
|
||||
/*
|
||||
* The GICv3 driver is initialized in EL3 and does not need
|
||||
* to be initialized again in SEL1. This is because the S-EL1
|
||||
* can use GIC system registers to manage interrupts and does
|
||||
* not need GIC interface base addresses to be configured.
|
||||
*/
|
||||
#if IMAGE_BL31
|
||||
gicv3_driver_init(&versal_gic_data);
|
||||
#endif
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Versal common helper to initialize the GIC. Only invoked by BL31
|
||||
*****************************************************************************/
|
||||
void __init plat_versal_gic_init(void)
|
||||
{
|
||||
gicv3_distif_init();
|
||||
gicv3_rdistif_init(plat_my_core_pos());
|
||||
gicv3_cpuif_enable(plat_my_core_pos());
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Versal common helper to enable the GIC CPU interface
|
||||
*****************************************************************************/
|
||||
void plat_versal_gic_cpuif_enable(void)
|
||||
{
|
||||
gicv3_cpuif_enable(plat_my_core_pos());
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Versal common helper to disable the GIC CPU interface
|
||||
*****************************************************************************/
|
||||
void plat_versal_gic_cpuif_disable(void)
|
||||
{
|
||||
gicv3_cpuif_disable(plat_my_core_pos());
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Versal common helper to initialize the per-cpu redistributor interface in
|
||||
* GICv3
|
||||
*****************************************************************************/
|
||||
void plat_versal_gic_pcpu_init(void)
|
||||
{
|
||||
gicv3_rdistif_init(plat_my_core_pos());
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Versal common helpers to power GIC redistributor interface
|
||||
*****************************************************************************/
|
||||
void plat_versal_gic_redistif_on(void)
|
||||
{
|
||||
gicv3_rdistif_on(plat_my_core_pos());
|
||||
}
|
||||
|
||||
void plat_versal_gic_redistif_off(void)
|
||||
{
|
||||
gicv3_rdistif_off(plat_my_core_pos());
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Versal common helper to save & restore the GICv3 on resume from system
|
||||
* suspend
|
||||
*****************************************************************************/
|
||||
void plat_versal_gic_save(void)
|
||||
{
|
||||
/*
|
||||
* If an ITS is available, save its context before
|
||||
* the Redistributor using:
|
||||
* gicv3_its_save_disable(gits_base, &its_ctx[i])
|
||||
* Additionnaly, an implementation-defined sequence may
|
||||
* be required to save the whole ITS state.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Save the GIC Redistributors and ITS contexts before the
|
||||
* Distributor context. As we only handle SYSTEM SUSPEND API,
|
||||
* we only need to save the context of the CPU that is issuing
|
||||
* the SYSTEM SUSPEND call, i.e. the current CPU.
|
||||
*/
|
||||
gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
|
||||
|
||||
/* Save the GIC Distributor context */
|
||||
gicv3_distif_save(&dist_ctx);
|
||||
|
||||
/*
|
||||
* From here, all the components of the GIC can be safely powered down
|
||||
* as long as there is an alternate way to handle wakeup interrupt
|
||||
* sources.
|
||||
*/
|
||||
}
|
||||
|
||||
void plat_versal_gic_resume(void)
|
||||
{
|
||||
/* Restore the GIC Distributor context */
|
||||
gicv3_distif_init_restore(&dist_ctx);
|
||||
|
||||
/*
|
||||
* Restore the GIC Redistributor and ITS contexts after the
|
||||
* Distributor context. As we only handle SYSTEM SUSPEND API,
|
||||
* we only need to restore the context of the CPU that issued
|
||||
* the SYSTEM SUSPEND call.
|
||||
*/
|
||||
gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
|
||||
|
||||
/*
|
||||
* If an ITS is available, restore its context after
|
||||
* the Redistributor using:
|
||||
* gicv3_its_restore(gits_base, &its_ctx[i])
|
||||
* An implementation-defined sequence may be required to
|
||||
* restore the whole ITS state. The ITS must also be
|
||||
* re-enabled after this sequence has been executed.
|
||||
*/
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef VERSAL_PRIVATE_H
|
||||
#define VERSAL_PRIVATE_H
|
||||
|
||||
#include <xlat_tables.h>
|
||||
|
||||
void versal_config_setup(void);
|
||||
|
||||
const mmap_region_t *plat_versal_get_mmap(void);
|
||||
|
||||
void plat_versal_gic_driver_init(void);
|
||||
void plat_versal_gic_init(void);
|
||||
void plat_versal_gic_cpuif_enable(void);
|
||||
void plat_versal_gic_cpuif_disable(void);
|
||||
void plat_versal_gic_pcpu_init(void);
|
||||
|
||||
unsigned int versal_calc_core_pos(u_register_t mpidr);
|
||||
|
||||
#endif /* VERSAL_PRIVATE_H */
|
||||
Loading…
Reference in New Issue