From eb20f04ef362d13fe6c230f308783bb1a9fa7b77 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Mon, 11 Mar 2019 15:36:07 +0000 Subject: [PATCH 1/2] bl2-el3: Fix exit to bl32 by ensuring a more complete write to SPSR Prior to entry into BL32 we set the SPSR by way of msr spsr, r1. This unfortunately only writes the bits f->[31:24] and c->[7:0]. This patch updates the bl2 exit path to write the x->[15:8] and c->[7:0] fields of the SPSR. For the purposes of initial setup of the SPSR the x and c fields should be sufficient and importantly will capture the necessary lower-order control bits that f:c alone do not. This is important to do to ensure the SPSR is set to the mode the platform intends prior to performing an eret. Fixes: b1d27b484f41 ("bl2-el3: Add BL2_EL3 image") Signed-off-by: Bryan O'Donoghue --- bl2/aarch32/bl2_el3_entrypoint.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bl2/aarch32/bl2_el3_entrypoint.S b/bl2/aarch32/bl2_el3_entrypoint.S index 35da133f7..9b4da6b13 100644 --- a/bl2/aarch32/bl2_el3_entrypoint.S +++ b/bl2/aarch32/bl2_el3_entrypoint.S @@ -78,7 +78,7 @@ func bl2_run_next_image */ ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] - msr spsr, r1 + msr spsr_xc, r1 /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ cps #MODE32_svc From 520f864e66f7e1253b294923196741536af41726 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Tue, 12 Mar 2019 12:09:51 +0000 Subject: [PATCH 2/2] bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to programming the lower-order 16 bits of the SPSR to populate into the CPSR on eret. The BL1 smc-handler code is identical and has the same shortfall in programming the SPSR from the platform defined struct entry_point_info->spsr. msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In order to ensure the 16 lower-order processor mode bits x->[15:8] and c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1. This change ensures we capture the x field, which we are interested in and not the f field which we are not. Fixes: f3b4914be3b4 ('AArch32: Add generic changes in BL1') Signed-off-by: Bryan O'Donoghue --- bl1/aarch32/bl1_exceptions.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bl1/aarch32/bl1_exceptions.S b/bl1/aarch32/bl1_exceptions.S index 6728278f8..f2af9ab5b 100644 --- a/bl1/aarch32/bl1_exceptions.S +++ b/bl1/aarch32/bl1_exceptions.S @@ -71,7 +71,7 @@ debug_loop: */ ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] - msr spsr, r1 + msr spsr_xc, r1 /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ cps #MODE32_svc