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Merge pull request #625 from antonio-nino-diaz-arm/an/delay-timer-v2 

Implement generic delay timer and use it on platforms
This commit is contained in:
danh-arm 2016-05-24 16:12:08 +01:00
parent d1d716531d 6704f425dd
commit e141aa0357
27 changed files with 138 additions and 72 deletions
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2
bl31/aarch64/bl31_arch_setup.c
View File

@ -44,7 +44,7 @@
void bl31_arch_setup(void)
{
/* Program the counter frequency */
write_cntfrq_el0(plat_get_syscnt_freq());
write_cntfrq_el0(plat_get_syscnt_freq2());
/* Initialize the cpu_ops pointer. */
init_cpu_ops();

4
docs/porting-guide.md
View File

@ -1529,10 +1529,10 @@ state. This function must return a pointer to the `entry_point_info` structure
(that was copied during `bl31_early_platform_setup()`) if the image exists. It
should return NULL otherwise.
### Function : plat_get_syscnt_freq() [mandatory]
### Function : plat_get_syscnt_freq2() [mandatory]
Argument : void
Return : uint64_t
Return : unsigned int
This function is used by the architecture setup code to retrieve the counter
frequency for the CPU's generic timer. This value will be programmed into the

3
docs/user-guide.md
View File

@ -492,6 +492,9 @@ map is explained in the [Firmware Design].
Trusted Firmware is configured for dual cluster topology and this option
can be used to override the default value.
* `FVP_USE_SP804_TIMER` : Use the SP804 timer instead of the Generic Timer
for functions that wait for an arbitrary time length (udelay and mdelay).
The default value is 0.
### Debugging options

23
drivers/delay_timer/delay_timer.c
View File

@ -48,19 +48,22 @@ void udelay(uint32_t usec)
(ops->clk_div != 0) &&
(ops->get_timer_value != 0));
uint32_t start, cnt, delta, delta_us;
uint32_t start, delta, total_delta;
assert(usec < UINT32_MAX / ops->clk_div);
/* counter is decreasing */
start = ops->get_timer_value();
total_delta = (usec * ops->clk_div) / ops->clk_mult;
do {
cnt = ops->get_timer_value();
if (cnt > start) {
delta = UINT32_MAX - cnt;
delta += start;
} else
delta = start - cnt;
delta_us = (delta * ops->clk_mult) / ops->clk_div;
} while (delta_us < usec);
/*
* If the timer value wraps around, the subtraction will
* overflow and it will still give the correct result.
*/
delta = start - ops->get_timer_value(); /* Decreasing counter */
} while (delta < total_delta);
}
/***********************************************************

61
plat/mediatek/mt8173/plat_delay_timer.c → drivers/delay_timer/generic_delay_timer.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -27,25 +27,56 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <delay_timer.h>
#include <mt8173_def.h>
static uint32_t plat_get_timer_value(void)
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
#include <delay_timer.h>
#include <platform.h>
/* Ticks elapsed in one second by a signal of 1 MHz */
#define MHZ_TICKS_PER_SEC 1000000
static timer_ops_t ops;
static uint32_t get_timer_value(void)
{
/* Generic delay timer implementation expects the timer to be a down
/*
* Generic delay timer implementation expects the timer to be a down
* counter. We apply bitwise NOT operator to the tick values returned
* by read_cntpct_el0() to simulate the down counter. */
* by read_cntpct_el0() to simulate the down counter. The value is
* clipped from 64 to 32 bits.
*/
return (uint32_t)(~read_cntpct_el0());
}
static const timer_ops_t plat_timer_ops = {
.get_timer_value = plat_get_timer_value,
.clk_mult = 1,
.clk_div = SYS_COUNTER_FREQ_IN_MHZ,
};
void plat_delay_timer_init(void)
void generic_delay_timer_init_args(uint32_t mult, uint32_t div)
{
timer_init(&plat_timer_ops);
ops.get_timer_value = get_timer_value;
ops.clk_mult = mult;
ops.clk_div = div;
timer_init(&ops);
VERBOSE("Generic delay timer configured with mult=%u and div=%u\n",
mult, div);
}
void generic_delay_timer_init(void)
{
/* Value in ticks */
unsigned int mult = MHZ_TICKS_PER_SEC;
/* Value in ticks per second (Hz) */
unsigned int div = plat_get_syscnt_freq2();
/* Reduce multiplier and divider by dividing them repeatedly by 10 */
while ((mult % 10 == 0) && (div % 10 == 0)) {
mult /= 10;
div /= 10;
}
generic_delay_timer_init_args(mult, div);
}

28
plat/rockchip/common/plat_delay_timer.c → include/drivers/generic_delay_timer.h
View File

@ -28,27 +28,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <delay_timer.h>
#include <platform_def.h>
#ifndef __GENERIC_DELAY_TIMER_H__
#define __GENERIC_DELAY_TIMER_H__
static uint32_t plat_get_timer_value(void)
{
/*
* Generic delay timer implementation expects the timer to be a down
* counter. We apply bitwise NOT operator to the tick values returned
* by read_cntpct_el0() to simulate the down counter.
*/
return (uint32_t)(~read_cntpct_el0());
}
#include <stdint.h>
static const timer_ops_t plat_timer_ops = {
.get_timer_value = plat_get_timer_value,
.clk_mult = 1,
.clk_div = SYS_COUNTER_FREQ_IN_MHZ,
};
void generic_delay_timer_init_args(uint32_t mult, uint32_t div);
void plat_delay_timer_init(void)
{
timer_init(&plat_timer_ops);
}
void generic_delay_timer_init(void);
#endif /* __GENERIC_DELAY_TIMER_H__ */

4
include/plat/common/platform.h
View File

@ -56,7 +56,9 @@ struct image_desc;
/*******************************************************************************
* Mandatory common functions
******************************************************************************/
unsigned long long plat_get_syscnt_freq(void);
unsigned long long plat_get_syscnt_freq(void) __deprecated;
unsigned int plat_get_syscnt_freq2(void);
int plat_get_image_source(unsigned int image_id,
uintptr_t *dev_handle,
uintptr_t *image_spec);

5
plat/arm/board/fvp/fvp_bl2_setup.c
View File

@ -28,6 +28,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <generic_delay_timer.h>
#include <mmio.h>
#include <plat_arm.h>
#include <sp804_delay_timer.h>
@ -48,6 +49,7 @@ void bl2_platform_setup(void)
{
arm_bl2_platform_setup();
#if FVP_USE_SP804_TIMER
/* Enable the clock override for SP804 timer 0, which means that no
* clock dividers are applied and the raw (35 MHz) clock will be used */
mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV);
@ -55,4 +57,7 @@ void bl2_platform_setup(void)
/* Initialize delay timer driver using SP804 dual timer 0 */
sp804_timer_init(V2M_SP804_TIMER0_BASE,
SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV);
#else
generic_delay_timer_init();
#endif /* FVP_USE_SP804_TIMER */
}

14
plat/arm/board/fvp/platform.mk
View File

@ -30,6 +30,11 @@
# Use the GICv3 driver on the FVP by default
FVP_USE_GIC_DRIVER := FVP_GICV3
# Use the SP804 timer instead of the generic one
FVP_USE_SP804_TIMER := 0
$(eval $(call assert_boolean,FVP_USE_SP804_TIMER))
$(eval $(call add_define,FVP_USE_SP804_TIMER))
# The FVP platform depends on this macro to build with correct GIC driver.
$(eval $(call add_define,FVP_USE_GIC_DRIVER))
@ -92,8 +97,7 @@ BL1_SOURCES += drivers/io/io_semihosting.c \
${FVP_INTERCONNECT_SOURCES}
BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \
drivers/io/io_semihosting.c \
BL2_SOURCES += drivers/io/io_semihosting.c \
drivers/delay_timer/delay_timer.c \
lib/semihosting/semihosting.c \
lib/semihosting/aarch64/semihosting_call.S \
@ -102,6 +106,12 @@ BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \
plat/arm/board/fvp/fvp_io_storage.c \
${FVP_SECURITY_SOURCES}
ifeq (${FVP_USE_SP804_TIMER},1)
BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c
else
BL2_SOURCES += drivers/delay_timer/generic_delay_timer.c
endif
BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \
${FVP_SECURITY_SOURCES}

16
plat/arm/common/aarch64/arm_common.c
View File

@ -29,6 +29,7 @@
*/
#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
#include <mmio.h>
#include <plat_arm.h>
@ -40,7 +41,14 @@ extern const mmap_region_t plat_arm_mmap[];
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_get_ns_image_entrypoint
#pragma weak plat_arm_get_mmap
/* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
* conflicts with the definition in plat/common. */
#if ERROR_DEPRECATED
#pragma weak plat_get_syscnt_freq2
#else
#pragma weak plat_get_syscnt_freq
#endif
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
@ -164,9 +172,16 @@ const mmap_region_t *plat_arm_get_mmap(void)
}
#ifdef ARM_SYS_CNTCTL_BASE
#if ERROR_DEPRECATED
unsigned int plat_get_syscnt_freq2(void)
{
unsigned int counter_base_frequency
#else
unsigned long long plat_get_syscnt_freq(void)
{
unsigned long long counter_base_frequency;
#endif /* ERROR_DEPRECATED */
/* Read the frequency from Frequency modes table */
counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF);
@ -177,4 +192,5 @@ unsigned long long plat_get_syscnt_freq(void)
return counter_base_frequency;
}
#endif /* ARM_SYS_CNTCTL_BASE */

14
plat/common/aarch64/plat_common.c
View File

@ -40,6 +40,9 @@
#pragma weak bl31_plat_enable_mmu
#pragma weak bl32_plat_enable_mmu
#pragma weak bl31_plat_runtime_setup
#if !ERROR_DEPRECATED
#pragma weak plat_get_syscnt_freq2
#endif /* ERROR_DEPRECATED */
void bl31_plat_enable_mmu(uint32_t flags)
{
@ -74,3 +77,14 @@ unsigned int platform_core_pos_helper(unsigned long mpidr)
}
#endif
#if !ERROR_DEPRECATED
unsigned int plat_get_syscnt_freq2(void)
{
unsigned long long freq = plat_get_syscnt_freq();
assert(freq >> 32 == 0);
return (unsigned int)freq;
}
#endif /* ERROR_DEPRECATED */

2
plat/mediatek/mt8173/aarch64/platform_common.c
View File

@ -84,7 +84,7 @@ const mmap_region_t plat_mmap[] = {
/* Define EL3 variants of the function initialising the MMU */
DEFINE_CONFIGURE_MMU_EL(3)
unsigned long long plat_get_syscnt_freq(void)
unsigned int plat_get_syscnt_freq2(void)
{
return SYS_COUNTER_FREQ_IN_TICKS;
}

5
plat/mediatek/mt8173/bl31_plat_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -32,6 +32,7 @@
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <generic_delay_timer.h>
#include <mcucfg.h>
#include <mmio.h>
#include <mtcmos.h>
@ -167,7 +168,7 @@ void bl31_platform_setup(void)
platform_setup_cpu();
platform_setup_sram();
plat_delay_timer_init();
generic_delay_timer_init();
/* Initialize the gic cpu and distributor interfaces */
plat_mt_gic_init();

1
plat/mediatek/mt8173/include/mt8173_def.h
View File

@ -83,7 +83,6 @@
* System counter frequency related constants
******************************************************************************/
#define SYS_COUNTER_FREQ_IN_TICKS 13000000
#define SYS_COUNTER_FREQ_IN_MHZ 13
/*******************************************************************************
* GIC-400 & interrupt handling related constants

2
plat/mediatek/mt8173/include/plat_private.h
View File

@ -51,6 +51,4 @@ void plat_mt_gic_init(void);
/* Declarations for plat_topology.c */
int mt_setup_topology(void);
void plat_delay_timer_init(void);
#endif /* __PLAT_PRIVATE_H__ */

2
plat/mediatek/mt8173/platform.mk
View File

@ -52,6 +52,7 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
drivers/arm/gic/gic_v3.c \
drivers/console/console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
@ -72,7 +73,6 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \
${MTK_PLAT_SOC}/drivers/timer/mt_cpuxgpt.c \
${MTK_PLAT_SOC}/drivers/uart/8250_console.S \
${MTK_PLAT_SOC}/plat_delay_timer.c \
${MTK_PLAT_SOC}/plat_mt_gic.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \

1
plat/nvidia/tegra/include/tegra_private.h
View File

@ -52,7 +52,6 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
/* Declarations for plat_setup.c */
const mmap_region_t *plat_get_mmio_map(void);
unsigned long long plat_get_syscnt_freq(void);
/* Declarations for plat_secondary.c */
void plat_secondary_setup(void);

2
plat/nvidia/tegra/soc/t132/plat_setup.c
View File

@ -74,7 +74,7 @@ const mmap_region_t *plat_get_mmio_map(void)
return tegra_mmap;
}
unsigned long long plat_get_syscnt_freq(void)
unsigned int plat_get_syscnt_freq2(void)
{
return 12000000;
}

2
plat/nvidia/tegra/soc/t210/plat_setup.c
View File

@ -80,7 +80,7 @@ const mmap_region_t *plat_get_mmio_map(void)
/*******************************************************************************
* Handler to get the System Counter Frequency
******************************************************************************/
unsigned long long plat_get_syscnt_freq(void)
unsigned int plat_get_syscnt_freq2(void)
{
return 19200000;
}

2
plat/rockchip/common/aarch64/platform_common.c
View File

@ -75,7 +75,7 @@ static const int cci_map[] = {
/* Define EL3 variants of the function initialising the MMU */
DEFINE_CONFIGURE_MMU_EL(3)
unsigned long long plat_get_syscnt_freq(void)
unsigned int plat_get_syscnt_freq2(void)
{
return SYS_COUNTER_FREQ_IN_TICKS;
}

3
plat/rockchip/common/bl31_plat_setup.c
View File

@ -33,6 +33,7 @@
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <generic_delay_timer.h>
#include <mmio.h>
#include <platform.h>
#include <plat_private.h>
@ -126,7 +127,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
******************************************************************************/
void bl31_platform_setup(void)
{
plat_delay_timer_init();
generic_delay_timer_init();
plat_rockchip_soc_init();
/* Initialize the gic cpu and distributor interfaces */

2
plat/rockchip/rk3368/platform.mk
View File

@ -58,13 +58,13 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/console/console.S \
drivers/ti/uart/16550_console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
lib/cpus/aarch64/cortex_a53.S \
plat/common/aarch64/platform_mp_stack.S \
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
${RK_PLAT_COMMON}/bl31_plat_setup.c \
${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \
${RK_PLAT_COMMON}/pmusram/pmu_sram.c \
${RK_PLAT_COMMON}/plat_delay_timer.c \
${RK_PLAT_COMMON}/plat_pm.c \
${RK_PLAT_COMMON}/plat_topology.c \
${RK_PLAT_COMMON}/aarch64/platform_common.c \

1
plat/rockchip/rk3368/rk3368_def.h
View File

@ -89,7 +89,6 @@
* System counter frequency related constants
******************************************************************************/
#define SYS_COUNTER_FREQ_IN_TICKS 24000000
#define SYS_COUNTER_FREQ_IN_MHZ 24
/******************************************************************************
* GIC-400 & interrupt handling related constants

2
plat/rockchip/rk3399/platform.mk
View File

@ -57,6 +57,7 @@ BL31_SOURCES += ${RK_GIC_SOURCES}
drivers/console/console.S \
drivers/ti/uart/16550_console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
plat/common/aarch64/platform_mp_stack.S \
@ -64,7 +65,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES}
${RK_PLAT_COMMON}/bl31_plat_setup.c \
${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \
${RK_PLAT_COMMON}/pmusram/pmu_sram.c \
${RK_PLAT_COMMON}/plat_delay_timer.c \
${RK_PLAT_COMMON}/plat_pm.c \
${RK_PLAT_COMMON}/plat_topology.c \
${RK_PLAT_COMMON}/aarch64/platform_common.c \

1
plat/rockchip/rk3399/rk3399_def.h
View File

@ -89,7 +89,6 @@
* System counter frequency related constants
******************************************************************************/
#define SYS_COUNTER_FREQ_IN_TICKS 24000000
#define SYS_COUNTER_FREQ_IN_MHZ 24
/* Base rockchip_platform compatible GIC memory map */
#define BASE_GICD_BASE (GIC500_BASE)

4
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
View File

@ -297,9 +297,9 @@ void zynqmp_config_setup(void)
mmio_write_32(IOU_SCNTRS_CONTROL, IOU_SCNTRS_CONTROL_EN);
}
unsigned long long plat_get_syscnt_freq(void)
unsigned int plat_get_syscnt_freq2(void)
{
unsigned long long counter_base_frequency;
unsigned int counter_base_frequency;
/* FIXME: Read the frequency from Frequency modes table */
counter_base_frequency = zynqmp_get_system_timer_freq();

4
services/std_svc/psci/psci_suspend.c
View File

@ -214,7 +214,7 @@ exit:
void psci_cpu_suspend_finish(unsigned int cpu_idx,
psci_power_state_t *state_info)
{
unsigned long long counter_freq;
unsigned int counter_freq;
unsigned int max_off_lvl;
/* Ensure we have been woken up from a suspended state */
@ -238,7 +238,7 @@ void psci_cpu_suspend_finish(unsigned int cpu_idx,
psci_do_pwrup_cache_maintenance();
/* Re-init the cntfrq_el0 register */
counter_freq = plat_get_syscnt_freq();
counter_freq = plat_get_syscnt_freq2();
write_cntfrq_el0(counter_freq);
/*