doc: Use proper note and warning annotations
The documentation contains plenty of notes and warnings. Enable special rendering of these blocks by converting the note prefix into a .. note:: annotation. Change-Id: I34e26ca6bf313d335672ab6c2645741900338822 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
This commit is contained in:
Paul Beesley
parent
f94102ba96
commit
e1c5026ac7
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@ -1186,7 +1186,8 @@ New features
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- Migrated to use SPDX[0] license identifiers to make software license
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auditing simpler.
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*NOTE:* Files that have been imported by FreeBSD have not been modified.
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.. note::
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Files that have been imported by FreeBSD have not been modified.
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[0]: https://spdx.org/
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@ -2205,7 +2206,8 @@ New features
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be used on the AEMv8 and Cortex-A57-A53 Base FVPs, as well as the Foundation
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FVP.
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NOTE: The software will not work on Version 1.0 of the Foundation FVP.
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.. note::
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The software will not work on Version 1.0 of the Foundation FVP.
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- Enabled third party contributions. Added a new contributing.md containing
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instructions for how to contribute and updated copyright text in all files
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@ -2236,15 +2238,18 @@ New features
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FIP from NOR flash, although some support for image loading using semi-
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hosting is retained.
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NOTE: Building a FIP by default is a non-backwards-compatible change.
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.. note::
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Building a FIP by default is a non-backwards-compatible change.
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NOTE: Generic BL2 code now loads a BL3-3 (non-trusted firmware) image into
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DRAM instead of expecting this to be pre-loaded at known location. This is
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also a non-backwards-compatible change.
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.. note::
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Generic BL2 code now loads a BL3-3 (non-trusted firmware) image into
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DRAM instead of expecting this to be pre-loaded at known location. This is
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also a non-backwards-compatible change.
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NOTE: Some non-trusted firmware (e.g. UEFI) will need to be rebuilt so that
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it knows the new location to execute from and no longer needs to copy
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particular code modules to DRAM itself.
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.. note::
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Some non-trusted firmware (e.g. UEFI) will need to be rebuilt so that
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it knows the new location to execute from and no longer needs to copy
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particular code modules to DRAM itself.
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- Reworked BL2 to BL3-1 handover interface. A new composite structure
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(bl31_args) holds the superset of information that needs to be passed from
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@ -2270,8 +2275,11 @@ New features
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Dispatcher (TSPD), which is loaded as an EL3 runtime service. The TSPD
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implements Secure Monitor functionality such as world switching and
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EL1 context management, and is responsible for communication with the TSP.
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NOTE: The TSPD does not yet contain support for secure world interrupts.
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NOTE: The TSP/TSPD is not built by default.
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.. note::
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The TSPD does not yet contain support for secure world interrupts.
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.. note::
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The TSP/TSPD is not built by default.
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Issues resolved since last release
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -193,7 +193,7 @@ priority assignment:
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6 and 5), the platform can partition into 4 secure priority ranges: ``0x0``,
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``0x20``, ``0x40``, and ``0x60``. See `Interrupt handling example`_.
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Note:
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.. note::
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The Arm GIC architecture requires that a GIC implementation that supports two
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security states must implement at least 32 priority levels; i.e., at least 5
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@ -215,7 +215,7 @@ priority level descriptors. Each entry in the array is of type
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``ehf_pri_desc_t``, and declares a priority level, and shall be populated by the
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``EHF_PRI_DESC()`` macro.
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Note:
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.. warning::
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The macro ``EHF_PRI_DESC()`` installs the descriptors in the array at a
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computed index, and not necessarily where the macro is placed in the array.
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@ -953,9 +953,11 @@ sources in the build for the various algorithms. Setting the variable to
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`rsa+ecdsa` enables support for both rsa and ecdsa algorithms in the mbedTLS
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library.
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Note: If code size is a concern, the build option ``MBEDTLS_SHA256_SMALLER`` can
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be defined in the platform Makefile. It will make mbed TLS use an implementation
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of SHA-256 with smaller memory footprint (~1.5 KB less) but slower (~30%).
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.. note::
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If code size is a concern, the build option ``MBEDTLS_SHA256_SMALLER`` can
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be defined in the platform Makefile. It will make mbed TLS use an
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implementation of SHA-256 with smaller memory footprint (~1.5 KB less) but
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slower (~30%).
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--------------
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@ -1141,8 +1141,10 @@ returning through EL3 and running the non-trusted firmware (BL33):
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``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to
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invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32
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entrypoint.
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NOTE: The Test SPD service included with TF-A provides one implementation
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of such a mechanism.
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.. note::
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The Test SPD service included with TF-A provides one implementation
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of such a mechanism.
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On completion BL32 returns control to BL31 via a SMC, and on receipt the
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SPD service handler invokes the synchronous call return mechanism to return
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@ -1675,8 +1677,9 @@ The location of the BL32 image will result in different memory maps. This is
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illustrated for both FVP and Juno in the following diagrams, using the TSP as
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an example.
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Note: Loading the BL32 image in TZC secured DRAM doesn't change the memory
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layout of the other images in Trusted SRAM.
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.. note::
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Loading the BL32 image in TZC secured DRAM doesn't change the memory
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layout of the other images in Trusted SRAM.
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CONFIG section in memory layouts shown below contains:
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@ -2215,8 +2218,9 @@ The default memory layout for each BL image is as follows:
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| Code |
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+-------------------+ BLx_BASE
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Note: The 2KB alignment for the exception vectors is an architectural
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requirement.
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.. note::
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The 2KB alignment for the exception vectors is an architectural
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requirement.
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The read-write data start on a new memory page so that they can be mapped with
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read-write permissions, whereas the code and read-only data below are configured
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@ -416,8 +416,9 @@ runtime.
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Test secure payload dispatcher behavior
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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**Note:** where this document discusses ``TSP_NS_INTR_ASYNC_PREEMPT`` as being
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``1``, the same results also apply when ``EL3_EXCEPTION_HANDLING`` is ``1``.
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.. note::
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Where this document discusses ``TSP_NS_INTR_ASYNC_PREEMPT`` as being
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``1``, the same results also apply when ``EL3_EXCEPTION_HANDLING`` is ``1``.
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The TSPD only handles Secure-EL1 interrupts and is provided with the following
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routing model at build time.
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@ -23,10 +23,11 @@ configuration, some of these steps might be unnecessary. The following sections
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guide the platform integrator by indicating which build options exclude which
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steps, depending on the capability of the platform.
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Note: If BL31 is used as the TF-A entry point instead of BL1, the diagram
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above is still relevant, as all these operations will occur in BL31 in
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this case. Please refer to section 6 "Using BL31 entrypoint as the reset
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address" for more information.
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.. note::
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If BL31 is used as the TF-A entry point instead of BL1, the diagram
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above is still relevant, as all these operations will occur in BL31 in
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this case. Please refer to section 6 "Using BL31 entrypoint as the reset
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address" for more information.
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Programmable CPU reset address
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------------------------------
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@ -141,8 +141,9 @@ if any of the steps fail.
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compared with the hash of the ROTPK read from the trusted root-key storage
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registers. If they match, the BL2 hash is read from the certificate.
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Note: the matching operation is platform specific and is currently
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unimplemented on the Arm development platforms.
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.. note::
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The matching operation is platform specific and is currently
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unimplemented on the Arm development platforms.
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- BL1 loads the BL2 image. Its hash is calculated and compared with the hash
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read from the certificate. Control is transferred to the BL2 image if all
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@ -331,7 +331,9 @@ must also be defined:
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SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
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corresponding to SCP_BL2U.
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NOTE: TF-A does not provide source code for this image.
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.. note::
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TF-A does not provide source code for this image.
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If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
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also be defined:
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@ -340,7 +342,9 @@ also be defined:
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Defines the base address in non-secure ROM where NS_BL1U executes.
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Must be aligned on a page-size boundary.
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NOTE: TF-A does not provide source code for this image.
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.. note::
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TF-A does not provide source code for this image.
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- **#define : NS_BL1U_IMAGE_ID**
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@ -354,7 +358,9 @@ be defined:
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Defines the base address in non-secure memory where NS_BL2U executes.
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Must be aligned on a page-size boundary.
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NOTE: TF-A does not provide source code for this image.
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.. note::
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TF-A does not provide source code for this image.
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- **#define : NS_BL2U_IMAGE_ID**
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@ -1000,8 +1006,9 @@ situation from which it cannot recover. This function must not return,
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and must be implemented in assembly because it may be called before the C
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environment is initialized.
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Note: The address from where it was called is stored in x30 (Link Register).
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The default implementation simply spins.
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.. note::
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The address from where it was called is stored in x30 (Link Register).
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The default implementation simply spins.
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Function : plat_get_bl_image_load_info()
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -1042,9 +1049,10 @@ value will weaken the protection as the attacker could easily write the right
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value as part of the attack most of the time. Therefore, it should return a
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true random number.
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Note: For the protection to be effective, the global data need to be placed at
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a lower address than the stack bases. Failure to do so would allow an attacker
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to overwrite the canary as part of the stack buffer overflow attack.
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.. warning::
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For the protection to be effective, the global data need to be placed at
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a lower address than the stack bases. Failure to do so would allow an
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attacker to overwrite the canary as part of the stack buffer overflow attack.
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Function : plat_flush_next_bl_params()
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -2564,10 +2572,12 @@ makefiles in order to benefit from them. By default, they will cause the crash
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output to be routed over the normal console infrastructure and get printed on
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consoles configured to output in crash state. ``console_set_scope()`` can be
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used to control whether a console is used for crash output.
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NOTE: Platforms are responsible for making sure that they only mark consoles for
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use in the crash scope that are able to support this, i.e. that are written in
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assembly and conform with the register clobber rules for putc() (x0-x2, x16-x17)
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and flush() (x0-x3, x16-x17) crash callbacks.
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.. note::
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Platforms are responsible for making sure that they only mark consoles for
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use in the crash scope that are able to support this, i.e. that are written
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in assembly and conform with the register clobber rules for putc()
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(x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
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In some cases (such as debugging very early crashes that happen before the
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normal boot console can be set up), platforms may want to control crash output
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@ -260,8 +260,9 @@ The ``cookie`` parameter to the handler is reserved for future use and can be
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ignored. The ``handle`` is returned by the SMC handler - completion of the
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handler function must always be via one of the ``SMC_RETn()`` macros.
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NOTE: The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow
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all of the above requirements yet.
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.. note::
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The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow
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all of the above requirements yet.
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Services that contain multiple sub-services
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-------------------------------------------
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@ -96,9 +96,10 @@ targets which both utilise the `checkpatch.pl` script that ships with the Linux
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source tree. The project also defines certain *checkpatch* options in the
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``.checkpatch.conf`` file in the top-level directory.
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**Note:** Checkpatch errors will gate upstream merging of pull requests.
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Checkpatch warnings will not gate merging but should be reviewed and fixed if
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possible.
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.. note::
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Checkpatch errors will gate upstream merging of pull requests.
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Checkpatch warnings will not gate merging but should be reviewed and fixed if
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possible.
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To check the entire source tree, you must first download copies of
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``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
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@ -718,8 +719,9 @@ Common build options
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of certificates in the FIP and FWU_FIP depends upon the value of the
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``GENERATE_COT`` option.
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Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
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already exist in disk, they will be overwritten without further notice.
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.. warning::
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This option depends on ``CREATE_KEYS`` to be enabled. If the keys
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already exist in disk, they will be overwritten without further notice.
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- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
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specifies the file that contains the Trusted World private key in PEM
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@ -739,8 +741,9 @@ Common build options
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interrupts to TSP allowing it to save its context and hand over
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synchronously to EL3 via an SMC.
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Note: when ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
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must also be set to ``1``.
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.. note::
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When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
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must also be set to ``1``.
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- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
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linker. When the ``LINKER`` build variable points to the armlink linker,
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@ -948,9 +951,10 @@ version to 2 is recommended for DS-5 versions older than 5.16.
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When debugging logic problems it might also be useful to disable all compiler
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optimizations by using ``-O0``.
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NOTE: Using ``-O0`` could cause output images to be larger and base addresses
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might need to be recalculated (see the **Memory layout on Arm development
|
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platforms** section in the `Firmware Design`_).
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.. warning::
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Using ``-O0`` could cause output images to be larger and base addresses
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might need to be recalculated (see the **Memory layout on Arm development
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platforms** section in the `Firmware Design`_).
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Extra debug options can be passed to the build system by setting ``CFLAGS`` or
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``LDFLAGS``:
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@ -1205,12 +1209,14 @@ images with support for these features:
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NS_BL2U=<path-to>/<ns_bl2u_image> \
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all fip fwu_fip
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Note: The BL2U image will be built by default and added to the FWU_FIP.
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The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
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to the command line above.
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.. note::
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The BL2U image will be built by default and added to the FWU_FIP.
|
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The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
|
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to the command line above.
|
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Note: Building and installing the non-secure and SCP FWU images (NS_BL1U,
|
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NS_BL2U and SCP_BL2U) is outside the scope of this document.
|
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.. note::
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Building and installing the non-secure and SCP FWU images (NS_BL1U,
|
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NS_BL2U and SCP_BL2U) is outside the scope of this document.
|
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The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
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Both the FIP and FWU_FIP will include the certificates corresponding to the
|
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@ -1252,21 +1258,26 @@ This section provides Juno and FVP specific instructions to build Trusted
|
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Firmware, obtain the additional required firmware, and pack it all together in
|
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a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
|
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Note: Pre-built binaries for AArch32 are available from Linaro Release 16.12
|
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onwards. Before that release, pre-built binaries are only available for AArch64.
|
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.. note::
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Pre-built binaries for AArch32 are available from Linaro Release 16.12
|
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onwards. Before that release, pre-built binaries are only available for
|
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AArch64.
|
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|
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Note: Follow the full instructions for one platform before switching to a
|
||||
different one. Mixing instructions for different platforms may result in
|
||||
corrupted binaries.
|
||||
.. warning::
|
||||
Follow the full instructions for one platform before switching to a
|
||||
different one. Mixing instructions for different platforms may result in
|
||||
corrupted binaries.
|
||||
|
||||
Note: The uboot image downloaded by the Linaro workspace script does not always
|
||||
match the uboot image packaged as BL33 in the corresponding fip file. It is
|
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recommended to use the version that is packaged in the fip file using the
|
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instructions below.
|
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.. warning::
|
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The uboot image downloaded by the Linaro workspace script does not always
|
||||
match the uboot image packaged as BL33 in the corresponding fip file. It is
|
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recommended to use the version that is packaged in the fip file using the
|
||||
instructions below.
|
||||
|
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Note: For the FVP, the kernel FDT is packaged in FIP during build and loaded
|
||||
by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
|
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section for more info on selecting the right FDT to use.
|
||||
.. note::
|
||||
For the FVP, the kernel FDT is packaged in FIP during build and loaded
|
||||
by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
|
||||
section for more info on selecting the right FDT to use.
|
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|
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#. Clean the working directory
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|
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@ -1291,12 +1302,14 @@ section for more info on selecting the right FDT to use.
|
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current working directory. The SCP_BL2 image corresponds to
|
||||
``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
|
||||
|
||||
Note: The fiptool will complain if the images to be unpacked already
|
||||
exist in the current directory. If that is the case, either delete those
|
||||
files or use the ``--force`` option to overwrite.
|
||||
.. note::
|
||||
The fiptool will complain if the images to be unpacked already
|
||||
exist in the current directory. If that is the case, either delete those
|
||||
files or use the ``--force`` option to overwrite.
|
||||
|
||||
Note: For AArch32, the instructions below assume that nt-fw.bin is a normal
|
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world boot loader that supports AArch32.
|
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.. note::
|
||||
For AArch32, the instructions below assume that nt-fw.bin is a
|
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normal world boot loader that supports AArch32.
|
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|
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#. Build TF-A images and create a new FIP for FVP
|
||||
|
||||
|
|
@ -1662,7 +1675,8 @@ The latest version of the AArch64 build of TF-A has been tested on the following
|
|||
Arm FVPs without shifted affinities, and that do not support threaded CPU cores
|
||||
(64-bit host machine only).
|
||||
|
||||
The FVP models used are Version 11.6 Build 45, unless otherwise stated.
|
||||
.. note::
|
||||
The FVP models used are Version 11.6 Build 45, unless otherwise stated.
|
||||
|
||||
- ``FVP_Base_AEMv8A-AEMv8A``
|
||||
- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
|
||||
|
|
@ -1699,30 +1713,36 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores
|
|||
- ``FVP_Base_AEMv8A-AEMv8A``
|
||||
- ``FVP_Base_Cortex-A32x4``
|
||||
|
||||
NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
|
||||
is not compatible with legacy GIC configurations. Therefore this FVP does not
|
||||
support these legacy GIC configurations.
|
||||
.. note::
|
||||
The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
|
||||
is not compatible with legacy GIC configurations. Therefore this FVP does not
|
||||
support these legacy GIC configurations.
|
||||
|
||||
NOTE: The build numbers quoted above are those reported by launching the FVP
|
||||
with the ``--version`` parameter.
|
||||
.. note::
|
||||
The build numbers quoted above are those reported by launching the FVP
|
||||
with the ``--version`` parameter.
|
||||
|
||||
NOTE: Linaro provides a ramdisk image in prebuilt FVP configurations and full
|
||||
file systems that can be downloaded separately. To run an FVP with a virtio
|
||||
file system image an additional FVP configuration option
|
||||
``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
|
||||
used.
|
||||
.. note::
|
||||
Linaro provides a ramdisk image in prebuilt FVP configurations and full
|
||||
file systems that can be downloaded separately. To run an FVP with a virtio
|
||||
file system image an additional FVP configuration option
|
||||
``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
|
||||
used.
|
||||
|
||||
NOTE: The software will not work on Version 1.0 of the Foundation FVP.
|
||||
The commands below would report an ``unhandled argument`` error in this case.
|
||||
.. note::
|
||||
The software will not work on Version 1.0 of the Foundation FVP.
|
||||
The commands below would report an ``unhandled argument`` error in this case.
|
||||
|
||||
NOTE: FVPs can be launched with ``--cadi-server`` option such that a
|
||||
CADI-compliant debugger (for example, Arm DS-5) can connect to and control its
|
||||
execution.
|
||||
.. note::
|
||||
FVPs can be launched with ``--cadi-server`` option such that a
|
||||
CADI-compliant debugger (for example, Arm DS-5) can connect to and control
|
||||
its execution.
|
||||
|
||||
NOTE: Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
|
||||
the internal synchronisation timings changed compared to older versions of the
|
||||
models. The models can be launched with ``-Q 100`` option if they are required
|
||||
to match the run time characteristics of the older versions.
|
||||
.. warning::
|
||||
Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
|
||||
the internal synchronisation timings changed compared to older versions of
|
||||
the models. The models can be launched with ``-Q 100`` option if they are
|
||||
required to match the run time characteristics of the older versions.
|
||||
|
||||
The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
|
||||
downloaded for free from `Arm's website`_.
|
||||
|
|
@ -1743,8 +1763,9 @@ be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
|
|||
a subset of the Base FVP components. For example, the Foundation FVP lacks
|
||||
CLCD and MMC support, and has only one CPU cluster.
|
||||
|
||||
Note: It is not recommended to use the FDTs built along the kernel because not
|
||||
all FDTs are available from there.
|
||||
.. note::
|
||||
It is not recommended to use the FDTs built along the kernel because not
|
||||
all FDTs are available from there.
|
||||
|
||||
The dynamic configuration capability is enabled in the firmware for FVPs.
|
||||
This means that the firmware can authenticate and load the FDT if present in
|
||||
|
|
@ -1851,8 +1872,9 @@ with 8 CPUs using the AArch64 build of TF-A.
|
|||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
|
||||
|
||||
Note: The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
|
||||
specific DTS for all the CPUs to be loaded.
|
||||
.. note::
|
||||
The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
|
||||
a specific DTS for all the CPUs to be loaded.
|
||||
|
||||
Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
|
@ -2010,8 +2032,9 @@ with 8 CPUs using the AArch32 build of TF-A.
|
|||
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
|
||||
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
|
||||
|
||||
Note: The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
|
||||
It should match the address programmed into the RVBAR register as well.
|
||||
.. note::
|
||||
The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
|
||||
It should match the address programmed into the RVBAR register as well.
|
||||
|
||||
Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
|
|
|||
|
|
@ -153,7 +153,8 @@ The latest version of the AArch64 build of TF-A has been tested on the following
|
|||
Arm FVPs without shifted affinities, and that do not support threaded CPU cores
|
||||
(64-bit host machine only).
|
||||
|
||||
The FVP models used are Version 11.5 Build 33, unless otherwise stated.
|
||||
.. note::
|
||||
The FVP models used are Version 11.5 Build 33, unless otherwise stated.
|
||||
|
||||
- ``FVP_Base_AEMv8A-AEMv8A``
|
||||
- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
|
||||
|
|
@ -190,7 +191,8 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores
|
|||
- ``FVP_Base_AEMv8A-AEMv8A``
|
||||
- ``FVP_Base_Cortex-A32x4``
|
||||
|
||||
NOTE: The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities.
|
||||
.. note::
|
||||
The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities.
|
||||
|
||||
The Foundation FVP can be downloaded free of charge. The Base FVPs can be
|
||||
licensed from Arm. See the `Arm FVP website`_.
|
||||
|
|
|
|||
|
|
@ -270,11 +270,12 @@ The following build options are supported:
|
|||
BL32_EXTRA1=tee-pager_v2.bin BL32_EXTRA2=tee-pageable_v2.bin``
|
||||
to put the binaries into the FIP.
|
||||
|
||||
Note: If OP-TEE is used it may be needed to add the following options to the
|
||||
Linux command line so that the USB driver doesn't use FIQs:
|
||||
``dwc_otg.fiq_enable=0 dwc_otg.fiq_fsm_enable=0 dwc_otg.nak_holdoff=0``.
|
||||
This will unfortunately reduce the performance of the USB driver. It is needed
|
||||
when using Raspbian, for example.
|
||||
.. warning::
|
||||
If OP-TEE is used it may be needed to add the following options to the
|
||||
Linux command line so that the USB driver doesn't use FIQs:
|
||||
``dwc_otg.fiq_enable=0 dwc_otg.fiq_fsm_enable=0 dwc_otg.nak_holdoff=0``.
|
||||
This will unfortunately reduce the performance of the USB driver. It is
|
||||
needed when using Raspbian, for example.
|
||||
|
||||
- ``TRUSTED_BOARD_BOOT``: This port supports TBB. Set this option to 1 to enable
|
||||
it. In order to use TBB, you might want to set ``GENERATE_COT=1`` to let the
|
||||
|
|
|
|||
|
|
@ -7,8 +7,9 @@ and provide feedback.
|
|||
|
||||
Some of the guidelines may also apply to other codebases.
|
||||
|
||||
**Note:** the existing TF codebase does not necessarily comply with all the
|
||||
below guidelines but the intent is for it to do so eventually.
|
||||
.. note::
|
||||
The existing TF codebase does not necessarily comply with all the
|
||||
below guidelines but the intent is for it to do so eventually.
|
||||
|
||||
Checkpatch overrides
|
||||
--------------------
|
||||
|
|
|
|||
|
|
@ -27,8 +27,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|||
|
||||
--------------
|
||||
|
||||
Note:
|
||||
Individual files contain the following tag instead of the full license text.
|
||||
.. note::
|
||||
Individual files contain the following tag instead of the full license text.
|
||||
|
||||
::
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue