intel: Extend SiP service to support mailbox's RSU
Introduce support for RSU that can be initiated through SMC calls. Added features as below: - RSU status - RSU update - RSU HPS notify - RSU get sub-partition Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c
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@ -14,6 +14,7 @@
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include "socfpga_mailbox.h"
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#include "socfpga_private.h"
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static entry_point_info_t bl32_image_ep_info;
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@ -107,6 +108,8 @@ void bl31_platform_setup(void)
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/* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
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mmio_write_64(PLAT_CPU_RELEASE_ADDR,
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(uint64_t)plat_secondary_cpus_bl31_entry);
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mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
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}
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const mmap_region_t plat_agilex_mmap[] = {
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@ -73,6 +73,29 @@
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/* Mailbox REBOOT commands */
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#define MBOX_CMD_REBOOT_HPS 71
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/* Mailbox RSU commands */
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#define MBOX_GET_SUBPARTITION_TABLE 90
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#define MBOX_RSU_STATUS 91
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#define MBOX_RSU_UPDATE 92
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/* Mailbox RSU macros */
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#define RSU_VERSION_ACMF BIT(8)
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#define RSU_VERSION_ACMF_MASK 0xff00
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/* HPS stage notify command */
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#define MBOX_HPS_STAGE_NOTIFY 93
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/* Execution states for HPS_STAGE_NOTIFY */
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#define HPS_EXECUTION_STATE_FSBL 0
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#define HPS_EXECUTION_STATE_SSBL 1
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#define HPS_EXECUTION_STATE_OS 2
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/* Mailbox reconfiguration commands */
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#define MBOX_CONFIG_STATUS 4
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#define MBOX_RECONFIG 6
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#define MBOX_RECONFIG_DATA 8
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#define MBOX_RECONFIG_STATUS 9
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/* Generic error handling */
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#define MBOX_TIMEOUT -2047
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#define MBOX_NO_RESPONSE -2
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@ -98,13 +121,6 @@
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#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
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#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
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/* Mailbox reconfiguration commands */
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#define MBOX_CONFIG_STATUS 4
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#define MBOX_RECONFIG 6
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#define MBOX_RECONFIG_DATA 8
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#define MBOX_RECONFIG_STATUS 9
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void mailbox_set_int(int interrupt_input);
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int mailbox_init(void);
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void mailbox_set_qspi_close(void);
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@ -122,4 +138,9 @@ void mailbox_clear_response(void);
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uint32_t intel_mailbox_get_config_status(uint32_t cmd);
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int intel_mailbox_is_fpga_not_ready(void);
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int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
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int mailbox_rsu_update(uint32_t *flash_offset);
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int mailbox_hps_stage_notify(uint32_t execution_stage);
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#endif /* SOCFPGA_MBOX_H */
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@ -267,6 +267,55 @@ void mailbox_reset_cold(void)
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mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_REBOOT_HPS, 0, 0, 0, NULL, 0);
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}
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int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len)
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{
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return mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_SUBPARTITION_TABLE,
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NULL, 0, 0, (uint32_t *)resp_buf,
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resp_buf_len);
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}
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struct rsu_status_info {
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uint64_t current_image;
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uint64_t fail_image;
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uint32_t state;
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uint32_t version;
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uint32_t error_location;
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uint32_t error_details;
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uint32_t retry_counter;
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};
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int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len)
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{
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int ret;
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struct rsu_status_info *info = (struct rsu_status_info *)resp_buf;
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info->retry_counter = ~0;
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ret = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_STATUS, NULL, 0, 0,
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(uint32_t *)resp_buf, resp_buf_len);
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if (ret < 0)
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return ret;
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if (info->retry_counter != ~0)
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if (!(info->version & RSU_VERSION_ACMF_MASK))
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info->version |= RSU_VERSION_ACMF;
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return ret;
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}
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int mailbox_rsu_update(uint32_t *flash_offset)
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{
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return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE,
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(uint32_t *)flash_offset, 2, 0, NULL, 0);
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}
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int mailbox_hps_stage_notify(uint32_t execution_stage)
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{
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return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HPS_STAGE_NOTIFY,
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&execution_stage, 1, 0, NULL, 0);
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}
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int mailbox_init(void)
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{
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int status = 0;
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@ -130,9 +130,14 @@ static void __dead2 socfpga_system_off(void)
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panic();
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}
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extern uint64_t intel_rsu_update_address;
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static void __dead2 socfpga_system_reset(void)
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{
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mailbox_reset_cold();
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if (intel_rsu_update_address)
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mailbox_rsu_update((uint32_t *)&intel_rsu_update_address);
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else
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mailbox_reset_cold();
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while (1)
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wfi();
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@ -365,6 +365,41 @@ uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask,
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return INTEL_SIP_SMC_STATUS_ERROR;
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}
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/* Intel Remote System Update (RSU) services */
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uint64_t intel_rsu_update_address;
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static uint32_t intel_rsu_status(uint64_t *respbuf, uint32_t respbuf_sz)
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{
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if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
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return INTEL_SIP_SMC_STATUS_ERROR;
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return INTEL_SIP_SMC_STATUS_OK;
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}
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static uint32_t intel_rsu_update(uint64_t update_address)
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{
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intel_rsu_update_address = update_address;
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return INTEL_SIP_SMC_STATUS_OK;
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}
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static uint32_t intel_rsu_notify(uint64_t execution_stage)
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{
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if (mailbox_hps_stage_notify((uint32_t)execution_stage) < 0)
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return INTEL_SIP_SMC_STATUS_ERROR;
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return INTEL_SIP_SMC_STATUS_OK;
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}
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static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
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uint32_t *ret_stat)
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{
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if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
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return INTEL_SIP_SMC_STATUS_ERROR;
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*ret_stat = respbuf[8];
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return INTEL_SIP_SMC_STATUS_OK;
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}
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/*
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* This function is responsible for handling all SiP calls from the NS world
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*/
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@ -381,6 +416,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
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uint32_t val = 0;
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uint32_t status = INTEL_SIP_SMC_STATUS_OK;
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uint32_t completed_addr[3];
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uint64_t rsu_respbuf[9];
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uint32_t count = 0;
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switch (smc_fid) {
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@ -446,6 +482,33 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
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(uint32_t)x3, &val);
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SMC_RET3(handle, status, val, x1);
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case INTEL_SIP_SMC_RSU_STATUS:
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status = intel_rsu_status(rsu_respbuf,
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ARRAY_SIZE(rsu_respbuf));
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if (status) {
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SMC_RET1(handle, status);
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} else {
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SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1],
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rsu_respbuf[2], rsu_respbuf[3]);
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}
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case INTEL_SIP_SMC_RSU_UPDATE:
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status = intel_rsu_update(x1);
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SMC_RET1(handle, status);
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case INTEL_SIP_SMC_RSU_NOTIFY:
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status = intel_rsu_notify(x1);
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SMC_RET1(handle, status);
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case INTEL_SIP_SMC_RSU_RETRY_COUNTER:
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status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
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ARRAY_SIZE(rsu_respbuf), &val);
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if (status) {
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SMC_RET1(handle, status);
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} else {
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SMC_RET2(handle, status, val);
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}
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default:
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return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
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cookie, handle, flags);
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@ -16,6 +16,7 @@
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include "socfpga_mailbox.h"
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#include "socfpga_private.h"
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#include "socfpga_reset_manager.h"
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#include "socfpga_system_manager.h"
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@ -115,6 +116,8 @@ void bl31_platform_setup(void)
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/* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
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mmio_write_64(PLAT_CPU_RELEASE_ADDR,
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(uint64_t)plat_secondary_cpus_bl31_entry);
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mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
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}
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const mmap_region_t plat_stratix10_mmap[] = {
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