Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
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johpow01
John_Powell
parent
6e886a4757
commit
e26c59d2c9
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@ -265,6 +265,9 @@ For Cortex-A78, the following errata build flags are defined :
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- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
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CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
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- ``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78
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CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
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For Neoverse N1, the following errata build flags are defined :
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- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2021, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -15,17 +15,18 @@
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
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#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
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#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
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@ -33,12 +34,12 @@
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
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#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
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#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
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#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
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#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
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#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
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#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
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#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
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#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
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#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
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#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
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#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
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#endif /* CORTEX_A78_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2021, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -31,7 +31,7 @@ func errata_a78_1688305_wa
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bl check_errata_1688305
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cbz x0, 1f
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mrs x1, CORTEX_A78_ACTLR2_EL1
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orr x1, x1, CORTEX_A78_ACTLR2_EL1_BIT_1
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orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1
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msr CORTEX_A78_ACTLR2_EL1, x1
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isb
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1:
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@ -44,6 +44,34 @@ func check_errata_1688305
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b cpu_rev_var_ls
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endfunc check_errata_1688305
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/* --------------------------------------------------
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* Errata Workaround for Cortex A78 Errata #1941498.
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* This applies to revisions r0p0, r1p0, and r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_1941498_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1941498
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cbz x0, 1f
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/* Set bit 8 in ECTLR_EL1 */
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mrs x1, CORTEX_A78_CPUECTLR_EL1
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orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8
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msr CORTEX_A78_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a78_1941498_wa
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func check_errata_1941498
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/* Check for revision <= r1p1, might need to be updated later. */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1941498
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78
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* -------------------------------------------------
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@ -58,6 +86,11 @@ func cortex_a78_reset_func
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bl errata_a78_1688305_wa
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#endif
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#if ERRATA_A78_1941498
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mov x0, x18
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bl errata_a78_1941498_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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@ -113,6 +146,7 @@ func cortex_a78_errata_report
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* checking functions of each errata.
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*/
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report_errata ERRATA_A78_1688305, cortex_a78, 1688305
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report_errata ERRATA_A78_1941498, cortex_a78, 1941498
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ldp x8, x30, [sp], #16
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ret
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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@ -294,6 +294,10 @@ ERRATA_A77_1925769 ?=0
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# to revisions r0p0 - r1p0 of the A78 cpu.
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ERRATA_A78_1688305 ?=0
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# Flag to apply erratum 1941498 workaround during reset. This erratum applies
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# to revisions r0p0, r1p0, and r1p1 of the A78 cpu.
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ERRATA_A78_1941498 ?=0
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# Flag to apply T32 CLREX workaround during reset. This erratum applies
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# only to r0p0 and r1p0 of the Neoverse N1 cpu.
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ERRATA_N1_1043202 ?=0
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@ -575,6 +579,10 @@ $(eval $(call add_define,ERRATA_A77_1925769))
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$(eval $(call assert_boolean,ERRATA_A78_1688305))
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$(eval $(call add_define,ERRATA_A78_1688305))
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# Process ERRATA_A78_1941498 flag
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$(eval $(call assert_boolean,ERRATA_A78_1941498))
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$(eval $(call add_define,ERRATA_A78_1941498))
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# Process ERRATA_N1_1043202 flag
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$(eval $(call assert_boolean,ERRATA_N1_1043202))
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$(eval $(call add_define,ERRATA_N1_1043202))
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