SPM: FVP: Introduce port of SPM
This initial port of the Secure Partitions Manager to FVP supports BL31 in both SRAM and Trusted DRAM. A document with instructions to build the SPM has been added. Change-Id: I4ea83ff0a659be77f2cd72eaf2302cdf8ba98b32 Co-authored-by: Douglas Raillard <douglas.raillard@arm.com> Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Co-authored-by: Achin Gupta <achin.gupta@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz
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@ -0,0 +1,59 @@
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ARM Trusted Firmware - SPM User Guide
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=====================================
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.. section-numbering::
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:suffix: .
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.. contents::
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This document briefly presents the Secure Partition Management (SPM) support in
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the Arm Trusted Firmware (TF), specifically focusing on how to build Arm TF with
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SPM support.
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Overview of the SPM software stack
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----------------------------------
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SPM is supported on the Arm FVP exclusively at the moment.
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It is not currently possible for BL31 to integrate SPM support and a Secure
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Payload Dispatcher (SPD) at the same time; they are mutually exclusive. In the
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SPM bootflow, a Secure Partition (SP) image executing at Secure-EL0 replaces the
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Secure Payload image executing at Secure-EL1 (e.g. a Trusted OS). Both are
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referred to as BL32.
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A working prototype of a SP has been implemented by repurposing the EDK2 code
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and tools, leveraging the concept of the *Standalone Management Mode (MM)* in
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the UEFI specification (see the PI v1.6 Volume 4: Management Mode Core
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Interface). This will be referred to as the *Standalone MM Secure Partition* in
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the rest of this document.
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Building TF with SPM support
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----------------------------
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To enable SPM support in the TF, the source code must be compiled with the build
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flag ``ENABLE_SPM=1``. On Arm platforms the build option ``ARM_BL31_IN_DRAM``
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can be used to select the location of BL31, both SRAM and DRAM are supported.
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Using the Standalone MM SP
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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First, build the Standalone MM Secure Partition. To build it, refer to the
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`instructions in the EDK2 repository`_.
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Then build TF with SPM support and include the Standalone MM Secure Partition
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image in the FIP:
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::
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BL32=path/to/standalone/mm/sp BL33=path/to/bl33.bin \
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make PLAT=fvp ENABLE_SPM=1 fip all
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--------------
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*Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.*
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.. _instructions in the EDK2 repository: https://github.com/tianocore/edk2-staging/blob/AArch64StandaloneMm/HowtoBuild.MD
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@ -52,7 +52,17 @@
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* They are also used for the dynamically mapped regions in the images that
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* enable dynamic memory mapping.
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*/
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#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
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#if defined(IMAGE_BL31)
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# if ENABLE_SPM
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# define PLAT_ARM_MMAP_ENTRIES 9
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# define MAX_XLAT_TABLES 7
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# define PLAT_SP_IMAGE_MMAP_REGIONS 7
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
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# else
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# define PLAT_ARM_MMAP_ENTRIES 7
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# define MAX_XLAT_TABLES 5
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# endif
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#elif defined(IMAGE_BL32)
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# define PLAT_ARM_MMAP_ENTRIES 7
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# define MAX_XLAT_TABLES 5
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#else
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@ -80,7 +90,11 @@
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* PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#if ENABLE_SPM
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#define PLAT_ARM_MAX_BL31_SIZE 0x28000
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#else
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#define PLAT_ARM_MAX_BL31_SIZE 0x1D000
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#endif
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#endif /* ARM_BOARD_OPTIMISE_MEM */
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@ -121,6 +121,11 @@
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V2M_IOFPGA_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/* Region equivalent to V2M_MAP_IOFPGA suitable for mapping at EL0 */
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#define V2M_MAP_IOFPGA_EL0 MAP_REGION_FLAT( \
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V2M_IOFPGA_BASE, \
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V2M_IOFPGA_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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#endif /* __V2M_DEF_H__ */
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@ -378,7 +378,13 @@
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* Trusted DRAM (if available) or the DRAM region secured by the TrustZone
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* controller.
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*/
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#if ARM_BL31_IN_DRAM
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#if ENABLE_SPM
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# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
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# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
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# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
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# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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ARM_AP_TZC_DRAM1_SIZE)
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#elif ARM_BL31_IN_DRAM
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# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
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PLAT_ARM_MAX_BL31_SIZE)
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# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
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@ -409,11 +415,14 @@
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# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
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#endif
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/* BL32 is mandatory in AArch32 */
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/*
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* BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
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* SPD and no SPM, as they are the only ones that can be used as BL32.
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*/
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#ifndef AARCH32
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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# if defined(SPD_none) && !ENABLE_SPM
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# undef BL32_BASE
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# endif
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#endif
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/*******************************************************************************
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@ -0,0 +1,105 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __ARM_SPM_DEF_H__
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#define __ARM_SPM_DEF_H__
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#include <arm_def.h>
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#include <platform_def.h>
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#include <utils_def.h>
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#include <xlat_tables_defs.h>
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/*
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* If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the
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* region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition
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* at the base of DRAM.
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*/
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#define ARM_SP_IMAGE_BASE BL32_BASE
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#define ARM_SP_IMAGE_LIMIT BL32_LIMIT
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/* The maximum size of the S-EL0 payload can be 3MB */
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#define ARM_SP_IMAGE_SIZE ULL(0x300000)
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#ifdef IMAGE_BL2
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/* SPM Payload memory. Mapped as RW in BL2. */
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#define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \
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ARM_SP_IMAGE_BASE, \
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ARM_SP_IMAGE_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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#ifdef IMAGE_BL31
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/* SPM Payload memory. Mapped as code in S-EL1 */
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#define ARM_SP_IMAGE_MMAP MAP_REGION2( \
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ARM_SP_IMAGE_BASE, \
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ARM_SP_IMAGE_BASE, \
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ARM_SP_IMAGE_SIZE, \
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MT_CODE | MT_SECURE | MT_USER, \
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PAGE_SIZE)
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#endif
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/*
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* Memory shared between EL3 and S-EL0. It is used by EL3 to push data into
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* S-EL0, so it is mapped with RW permission from EL3 and with RO permission
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* from S-EL0. Placed after SPM Payload memory.
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*/
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#define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE)
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#define PLAT_SPM_BUF_SIZE ULL(0x100000)
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#define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_SIZE, \
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MT_RW_DATA | MT_SECURE)
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#define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_BASE, \
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PLAT_SPM_BUF_SIZE, \
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MT_RO_DATA | MT_SECURE | MT_USER,\
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PAGE_SIZE)
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/*
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* Memory shared between Normal world and S-EL0 for passing data during service
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* requests. Mapped as RW and NS. Placed after the shared memory between EL3 and
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* S-EL0.
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*/
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#define ARM_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)
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#define ARM_SP_IMAGE_NS_BUF_SIZE ULL(0x10000)
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#define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \
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ARM_SP_IMAGE_NS_BUF_BASE, \
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ARM_SP_IMAGE_NS_BUF_BASE, \
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ARM_SP_IMAGE_NS_BUF_SIZE, \
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MT_RW_DATA | MT_NS | MT_USER, \
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PAGE_SIZE)
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/*
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* RW memory, which uses the remaining Trusted DRAM. Placed after the memory
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* shared between Secure and Non-secure worlds. First there is the stack memory
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* for all CPUs and then there is the common heap memory. Both are mapped with
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* RW permissions.
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*/
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#define PLAT_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \
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ARM_SP_IMAGE_NS_BUF_SIZE)
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#define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000)
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#define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \
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PLAT_SP_IMAGE_STACK_PCPU_SIZE)
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#define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \
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ARM_SP_IMAGE_STACK_TOTAL_SIZE)
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#define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE)
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#define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \
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PLAT_SP_IMAGE_STACK_BASE, \
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PLAT_SP_IMAGE_STACK_BASE, \
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(ARM_SP_IMAGE_LIMIT - \
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PLAT_SP_IMAGE_STACK_BASE), \
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MT_RW_DATA | MT_SECURE | MT_USER,\
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PAGE_SIZE)
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/* Total number of memory regions with distinct properties */
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#define ARM_SP_IMAGE_NUM_MEM_REGIONS 6
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/* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */
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#define PLAT_SPM_COOKIE_0 ULL(0)
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#define PLAT_SPM_COOKIE_1 ULL(0)
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#endif /* __ARM_SPM_DEF_H__ */
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@ -6,6 +6,7 @@
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#include <arm_config.h>
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#include <arm_def.h>
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#include <arm_spm_def.h>
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#include <assert.h>
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#include <cci.h>
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#include <ccn.h>
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@ -13,6 +14,7 @@
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#include <gicv2.h>
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#include <mmio.h>
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#include <plat_arm.h>
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#include <secure_partition.h>
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#include <v2m_def.h>
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#include "../fvp_def.h"
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@ -89,6 +91,9 @@ const mmap_region_t plat_arm_mmap[] = {
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/* To access the Root of Trust Public Key registers. */
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MAP_DEVICE2,
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#endif
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#if ENABLE_SPM
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ARM_SP_IMAGE_MMAP,
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#endif
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#if ARM_BL31_IN_DRAM
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ARM_MAP_BL31_SEC_DRAM,
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#endif
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@ -114,8 +119,22 @@ const mmap_region_t plat_arm_mmap[] = {
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MAP_DEVICE0,
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MAP_DEVICE1,
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ARM_V2M_MAP_MEM_PROTECT,
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#if ENABLE_SPM
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ARM_SPM_BUF_EL3_MMAP,
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#endif
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{0}
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};
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#if ENABLE_SPM && defined(IMAGE_BL31)
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const mmap_region_t plat_arm_secure_partition_mmap[] = {
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V2M_MAP_IOFPGA_EL0, /* for the UART */
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ARM_SP_IMAGE_MMAP,
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ARM_SP_IMAGE_NS_BUF_MMAP,
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ARM_SP_IMAGE_RW_MMAP,
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ARM_SPM_BUF_EL0_MMAP,
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{0}
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};
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#endif
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#endif
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#ifdef IMAGE_BL32
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const mmap_region_t plat_arm_mmap[] = {
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@ -156,6 +175,57 @@ static unsigned int get_interconnect_master(void)
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}
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#endif
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#if ENABLE_SPM && defined(IMAGE_BL31)
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/*
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* Boot information passed to a secure partition during initialisation. Linear
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* indices in MP information will be filled at runtime.
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*/
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static secure_partition_mp_info_t sp_mp_info[] = {
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[0] = {0x80000000, 0},
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[1] = {0x80000001, 0},
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[2] = {0x80000002, 0},
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[3] = {0x80000003, 0},
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[4] = {0x80000100, 0},
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[5] = {0x80000101, 0},
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[6] = {0x80000102, 0},
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[7] = {0x80000103, 0},
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};
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const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
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.h.type = PARAM_SP_IMAGE_BOOT_INFO,
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.h.version = VERSION_1,
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.h.size = sizeof(secure_partition_boot_info_t),
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.h.attr = 0,
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.sp_mem_base = ARM_SP_IMAGE_BASE,
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.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
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.sp_image_base = ARM_SP_IMAGE_BASE,
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.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
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.sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
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.sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE,
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.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
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.sp_image_size = ARM_SP_IMAGE_SIZE,
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.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
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.sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
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.sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE,
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.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
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.num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
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.num_cpus = PLATFORM_CORE_COUNT,
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.mp_info = &sp_mp_info[0],
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};
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const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
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{
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return plat_arm_secure_partition_mmap;
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}
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const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
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void *cookie)
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{
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return &plat_arm_secure_partition_boot_info;
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}
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#endif
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/*******************************************************************************
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* A single boot loader stack is expected to work on both the Foundation FVP
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* models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
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@ -11,6 +11,7 @@
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#include <mmio.h>
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#include <plat_arm.h>
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#include <platform_def.h>
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#include <secure_partition.h>
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extern const mmap_region_t plat_arm_mmap[];
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@ -79,6 +80,14 @@ void arm_setup_page_tables(uintptr_t total_base,
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MT_DEVICE | MT_RW | MT_SECURE);
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#endif
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#if ENABLE_SPM && defined(IMAGE_BL31)
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/* The address of the following region is calculated by the linker. */
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mmap_add_region(SP_IMAGE_XLAT_TABLES_START,
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SP_IMAGE_XLAT_TABLES_START,
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SP_IMAGE_XLAT_TABLES_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE);
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#endif
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/* Now (re-)map the platform-specific memory regions */
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mmap_add(plat_arm_get_mmap());
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@ -1,10 +1,11 @@
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/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arm_def.h>
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#include <arm_spm_def.h>
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#include <debug.h>
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#include <platform_def.h>
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#include <tzc400.h>
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@ -56,9 +57,26 @@ void arm_tzc400_setup(void)
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ARM_DRAM2_BASE, ARM_DRAM2_END,
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ARM_TZC_NS_DRAM_S_ACCESS,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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#else
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#if ENABLE_SPM
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/*
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* Region 4 set to cover Non-Secure access to the communication buffer
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* shared with the Secure world.
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*/
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tzc400_configure_region(PLAT_ARM_TZC_FILTERS,
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4,
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ARM_SP_IMAGE_NS_BUF_BASE,
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(ARM_SP_IMAGE_NS_BUF_BASE +
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ARM_SP_IMAGE_NS_BUF_SIZE) - 1,
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TZC_REGION_S_NONE,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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#endif
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#else /* if defined(EL3_PAYLOAD_BASE) */
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/* Allow secure access only to DRAM for EL3 payloads. */
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tzc400_configure_region0(TZC_REGION_S_RDWR, 0);
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#endif /* EL3_PAYLOAD_BASE */
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/*
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||||
|
|
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|||
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Reference in New Issue