Merge pull request #1732 from jollysxilinx/integration
plat: xilinx: Clock and PLL EEMI API Support
This commit is contained in:
commit
e33aca3e1d
File diff suppressed because it is too large
Load Diff
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@ -56,7 +56,7 @@
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#define END_OF_CLK "END_OF_CLK"
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#define END_OF_CLK "END_OF_CLK"
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//CLock Ids
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//CLock Ids
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enum {
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enum clock_id {
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CLK_IOPLL,
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CLK_IOPLL,
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CLK_RPLL,
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CLK_RPLL,
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CLK_APLL,
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CLK_APLL,
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@ -160,6 +160,7 @@ enum {
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CLK_VPLL_POST_SRC,
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CLK_VPLL_POST_SRC,
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CLK_CAN0_MIO,
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CLK_CAN0_MIO,
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CLK_CAN1_MIO,
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CLK_CAN1_MIO,
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CLK_ACPU_FULL,
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END_OF_OUTPUT_CLKS,
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END_OF_OUTPUT_CLKS,
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};
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};
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@ -275,6 +276,10 @@ enum {
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#define TYPE_DIV2 5U
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#define TYPE_DIV2 5U
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#define TYPE_GATE 6U
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#define TYPE_GATE 6U
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struct pm_pll;
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struct pm_pll *pm_clock_get_pll(enum clock_id clock_id);
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struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id);
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uint8_t pm_clock_has_div(unsigned int clock_id, enum pm_clock_div_id div_id);
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enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
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enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
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enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks);
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enum pm_ret_status pm_api_clock_get_num_clocks(unsigned int *nclocks);
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@ -289,29 +294,24 @@ enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id,
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uint32_t *parents);
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uint32_t *parents);
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enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id,
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enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id,
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uint32_t *attr);
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uint32_t *attr);
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enum pm_ret_status pm_api_clock_enable(unsigned int clock_id);
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enum pm_ret_status pm_api_clock_disable(unsigned int clock_id);
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enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id,
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enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id,
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enum pm_node_id *node_id);
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unsigned int *state);
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enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id);
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enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id,
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unsigned int divider);
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enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll);
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enum pm_ret_status pm_api_clock_getdivider(unsigned int clock_id,
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enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll);
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unsigned int *divider);
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enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll,
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enum pm_ret_status pm_api_clock_setrate(unsigned int clock_id,
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unsigned int *state);
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uint64_t rate);
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enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll,
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enum pm_ret_status pm_api_clock_getrate(unsigned int clock_id,
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enum clock_id clock_id,
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uint64_t *rate);
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unsigned int parent_index);
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enum pm_ret_status pm_api_clock_setparent(unsigned int clock_id,
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enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll,
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unsigned int parent_idx);
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enum clock_id clock_id,
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enum pm_ret_status pm_api_clock_getparent(unsigned int clock_id,
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unsigned int *parent_index);
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unsigned int *parent_idx);
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enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id,
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enum pm_ret_status pm_api_clk_set_pll_mode(unsigned int pll,
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unsigned int mode);
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unsigned int mode);
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enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id,
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enum pm_ret_status pm_api_clk_get_pll_mode(unsigned int pll,
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unsigned int *mode);
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unsigned int *mode);
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enum pm_ret_status pm_api_clk_set_pll_frac_data(unsigned int pll,
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unsigned int data);
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enum pm_ret_status pm_api_clk_get_pll_frac_data(unsigned int pll,
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unsigned int *data);
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#endif /* PM_API_CLOCK_H */
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#endif /* PM_API_CLOCK_H */
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@ -333,7 +333,7 @@ reset_release:
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/**
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/**
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* pm_ioctl_set_pll_frac_mode() - Ioctl function for
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* pm_ioctl_set_pll_frac_mode() - Ioctl function for
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* setting pll mode
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* setting pll mode
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* @pll PLL id
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* @pll PLL clock id
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* @mode Mode fraction/integar
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* @mode Mode fraction/integar
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*
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*
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* This function sets PLL mode
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* This function sets PLL mode
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@ -343,13 +343,13 @@ reset_release:
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static enum pm_ret_status pm_ioctl_set_pll_frac_mode
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static enum pm_ret_status pm_ioctl_set_pll_frac_mode
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(unsigned int pll, unsigned int mode)
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(unsigned int pll, unsigned int mode)
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{
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{
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return pm_api_clk_set_pll_mode(pll, mode);
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return pm_clock_set_pll_mode(pll, mode);
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}
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}
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/**
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/**
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* pm_ioctl_get_pll_frac_mode() - Ioctl function for
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* pm_ioctl_get_pll_frac_mode() - Ioctl function for
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* getting pll mode
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* getting pll mode
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* @pll PLL id
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* @pll PLL clock id
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* @mode Mode fraction/integar
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* @mode Mode fraction/integar
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*
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*
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* This function return current PLL mode
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* This function return current PLL mode
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@ -359,13 +359,13 @@ static enum pm_ret_status pm_ioctl_set_pll_frac_mode
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static enum pm_ret_status pm_ioctl_get_pll_frac_mode
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static enum pm_ret_status pm_ioctl_get_pll_frac_mode
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(unsigned int pll, unsigned int *mode)
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(unsigned int pll, unsigned int *mode)
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{
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{
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return pm_api_clk_get_pll_mode(pll, mode);
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return pm_clock_get_pll_mode(pll, mode);
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}
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}
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/**
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/**
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* pm_ioctl_set_pll_frac_data() - Ioctl function for
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* pm_ioctl_set_pll_frac_data() - Ioctl function for
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* setting pll fraction data
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* setting pll fraction data
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* @pll PLL id
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* @pll PLL clock id
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* @data fraction data
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* @data fraction data
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*
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*
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* This function sets fraction data.
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* This function sets fraction data.
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@ -376,13 +376,21 @@ static enum pm_ret_status pm_ioctl_get_pll_frac_mode
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static enum pm_ret_status pm_ioctl_set_pll_frac_data
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static enum pm_ret_status pm_ioctl_set_pll_frac_data
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(unsigned int pll, unsigned int data)
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(unsigned int pll, unsigned int data)
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{
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{
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return pm_api_clk_set_pll_frac_data(pll, data);
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enum pm_node_id pll_nid;
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enum pm_ret_status status;
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/* Get PLL node ID using PLL clock ID */
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status = pm_clock_get_pll_node_id(pll, &pll_nid);
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if (status != PM_RET_SUCCESS)
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return status;
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return pm_pll_set_parameter(pll_nid, PM_PLL_PARAM_DATA, data);
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}
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}
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/**
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/**
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* pm_ioctl_get_pll_frac_data() - Ioctl function for
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* pm_ioctl_get_pll_frac_data() - Ioctl function for
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* getting pll fraction data
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* getting pll fraction data
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* @pll PLL id
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* @pll PLL clock id
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* @data fraction data
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* @data fraction data
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*
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*
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* This function returns fraction data value.
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* This function returns fraction data value.
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@ -392,7 +400,15 @@ static enum pm_ret_status pm_ioctl_set_pll_frac_data
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static enum pm_ret_status pm_ioctl_get_pll_frac_data
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static enum pm_ret_status pm_ioctl_get_pll_frac_data
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(unsigned int pll, unsigned int *data)
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(unsigned int pll, unsigned int *data)
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{
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{
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return pm_api_clk_get_pll_frac_data(pll, data);
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enum pm_node_id pll_nid;
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enum pm_ret_status status;
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/* Get PLL node ID using PLL clock ID */
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status = pm_clock_get_pll_node_id(pll, &pll_nid);
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if (status != PM_RET_SUCCESS)
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return status;
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return pm_pll_get_parameter(pll_nid, PM_PLL_PARAM_DATA, data);
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}
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}
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/**
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/**
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@ -844,6 +844,36 @@ static enum pm_ret_status pm_clock_get_attributes(unsigned int clock_id,
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return pm_api_clock_get_attributes(clock_id, attr);
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return pm_api_clock_get_attributes(clock_id, attr);
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}
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}
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/**
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* pm_clock_gate() - Configure clock gate
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* @clock_id Id of the clock to be configured
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* @enable Flag 0=disable (gate the clock), !0=enable (activate the clock)
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*
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* @return Error if an argument is not valid or status as returned by the
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* PM controller (PMU)
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*/
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static enum pm_ret_status pm_clock_gate(unsigned int clock_id,
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unsigned char enable)
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{
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uint32_t payload[PAYLOAD_ARG_CNT];
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enum pm_ret_status status;
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enum pm_api_id api_id;
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/* Check if clock ID is valid and return an error if it is not */
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status = pm_clock_id_is_valid(clock_id);
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if (status != PM_RET_SUCCESS)
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return status;
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if (enable)
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api_id = PM_CLOCK_ENABLE;
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else
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api_id = PM_CLOCK_DISABLE;
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/* Send request to the PMU */
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PM_PACK_PAYLOAD2(payload, api_id, clock_id);
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return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
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}
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/**
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/**
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* pm_clock_enable() - Enable the clock for given id
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* pm_clock_enable() - Enable the clock for given id
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* @clock_id: Id of the clock to be enabled
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* @clock_id: Id of the clock to be enabled
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@ -851,12 +881,20 @@ static enum pm_ret_status pm_clock_get_attributes(unsigned int clock_id,
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* This function is used by master to enable the clock
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* This function is used by master to enable the clock
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* including peripherals and PLL clocks.
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* including peripherals and PLL clocks.
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*
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*
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* Return: Returns status, either success or error+reason.
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* @return: Error if an argument is not valid or status as returned by the
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* pm_clock_gate
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*/
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*/
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enum pm_ret_status pm_clock_enable(unsigned int clock_id)
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enum pm_ret_status pm_clock_enable(unsigned int clock_id)
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{
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{
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return pm_api_clock_enable(clock_id);
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struct pm_pll *pll;
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/* First try to handle it as a PLL */
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pll = pm_clock_get_pll(clock_id);
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if (pll)
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return pm_clock_pll_enable(pll);
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/* It's an on-chip clock, PMU should configure clock's gate */
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return pm_clock_gate(clock_id, 1);
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}
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}
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/**
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/**
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@ -866,12 +904,20 @@ enum pm_ret_status pm_clock_enable(unsigned int clock_id)
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* This function is used by master to disable the clock
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* This function is used by master to disable the clock
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* including peripherals and PLL clocks.
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* including peripherals and PLL clocks.
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*
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*
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* Return: Returns status, either success or error+reason.
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* @return: Error if an argument is not valid or status as returned by the
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* pm_clock_gate
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*/
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*/
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enum pm_ret_status pm_clock_disable(unsigned int clock_id)
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enum pm_ret_status pm_clock_disable(unsigned int clock_id)
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{
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{
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return pm_api_clock_disable(clock_id);
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struct pm_pll *pll;
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/* First try to handle it as a PLL */
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pll = pm_clock_get_pll(clock_id);
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if (pll)
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return pm_clock_pll_disable(pll);
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/* It's an on-chip clock, PMU should configure clock's gate */
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return pm_clock_gate(clock_id, 0);
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}
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}
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/**
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/**
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@ -887,7 +933,23 @@ enum pm_ret_status pm_clock_disable(unsigned int clock_id)
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enum pm_ret_status pm_clock_getstate(unsigned int clock_id,
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enum pm_ret_status pm_clock_getstate(unsigned int clock_id,
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unsigned int *state)
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unsigned int *state)
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{
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{
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return pm_api_clock_getstate(clock_id, state);
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struct pm_pll *pll;
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uint32_t payload[PAYLOAD_ARG_CNT];
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enum pm_ret_status status;
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/* First try to handle it as a PLL */
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pll = pm_clock_get_pll(clock_id);
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if (pll)
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return pm_clock_pll_get_state(pll, state);
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/* Check if clock ID is a valid on-chip clock */
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status = pm_clock_id_is_valid(clock_id);
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if (status != PM_RET_SUCCESS)
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return status;
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/* Send request to the PMU */
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PM_PACK_PAYLOAD2(payload, PM_CLOCK_GETSTATE, clock_id);
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return pm_ipi_send_sync(primary_proc, payload, state, 1);
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}
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}
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/**
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/**
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@ -903,7 +965,37 @@ enum pm_ret_status pm_clock_getstate(unsigned int clock_id,
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enum pm_ret_status pm_clock_setdivider(unsigned int clock_id,
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enum pm_ret_status pm_clock_setdivider(unsigned int clock_id,
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unsigned int divider)
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unsigned int divider)
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{
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{
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return pm_api_clock_setdivider(clock_id, divider);
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enum pm_ret_status status;
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enum pm_node_id nid;
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enum pm_clock_div_id div_id;
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uint32_t payload[PAYLOAD_ARG_CNT];
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const uint32_t div0 = 0xFFFF0000;
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const uint32_t div1 = 0x0000FFFF;
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uint32_t val;
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/* Get PLL node ID using PLL clock ID */
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status = pm_clock_get_pll_node_id(clock_id, &nid);
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if (status == PM_RET_SUCCESS)
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return pm_pll_set_parameter(nid, PM_PLL_PARAM_FBDIV, divider);
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/* Check if clock ID is a valid on-chip clock */
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status = pm_clock_id_is_valid(clock_id);
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if (status != PM_RET_SUCCESS)
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return status;
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if (div0 == (divider & div0)) {
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div_id = PM_CLOCK_DIV0_ID;
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val = divider & ~div0;
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} else if (div1 == (divider & div1)) {
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div_id = PM_CLOCK_DIV1_ID;
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val = (divider & ~div1) >> 16;
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} else {
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return PM_RET_ERROR_ARGS;
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}
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/* Send request to the PMU */
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PM_PACK_PAYLOAD4(payload, PM_CLOCK_SETDIVIDER, clock_id, div_id, val);
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return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
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}
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}
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/**
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/**
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@ -919,7 +1011,42 @@ enum pm_ret_status pm_clock_setdivider(unsigned int clock_id,
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enum pm_ret_status pm_clock_getdivider(unsigned int clock_id,
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enum pm_ret_status pm_clock_getdivider(unsigned int clock_id,
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unsigned int *divider)
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unsigned int *divider)
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{
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{
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return pm_api_clock_getdivider(clock_id, divider);
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enum pm_ret_status status;
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enum pm_node_id nid;
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uint32_t payload[PAYLOAD_ARG_CNT];
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uint32_t val;
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/* Get PLL node ID using PLL clock ID */
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status = pm_clock_get_pll_node_id(clock_id, &nid);
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if (status == PM_RET_SUCCESS)
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return pm_pll_get_parameter(nid, PM_PLL_PARAM_FBDIV, divider);
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/* Check if clock ID is a valid on-chip clock */
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status = pm_clock_id_is_valid(clock_id);
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if (status != PM_RET_SUCCESS)
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return status;
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if (pm_clock_has_div(clock_id, PM_CLOCK_DIV0_ID)) {
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/* Send request to the PMU to get div0 */
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PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id,
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PM_CLOCK_DIV0_ID);
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status = pm_ipi_send_sync(primary_proc, payload, &val, 1);
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if (status != PM_RET_SUCCESS)
|
||||||
|
return status;
|
||||||
|
*divider = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (pm_clock_has_div(clock_id, PM_CLOCK_DIV1_ID)) {
|
||||||
|
/* Send request to the PMU to get div1 */
|
||||||
|
PM_PACK_PAYLOAD3(payload, PM_CLOCK_GETDIVIDER, clock_id,
|
||||||
|
PM_CLOCK_DIV1_ID);
|
||||||
|
status = pm_ipi_send_sync(primary_proc, payload, &val, 1);
|
||||||
|
if (status != PM_RET_SUCCESS)
|
||||||
|
return status;
|
||||||
|
*divider |= val << 16;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -934,7 +1061,7 @@ enum pm_ret_status pm_clock_getdivider(unsigned int clock_id,
|
||||||
enum pm_ret_status pm_clock_setrate(unsigned int clock_id,
|
enum pm_ret_status pm_clock_setrate(unsigned int clock_id,
|
||||||
uint64_t rate)
|
uint64_t rate)
|
||||||
{
|
{
|
||||||
return pm_api_clock_setrate(clock_id, rate);
|
return PM_RET_ERROR_NOTSUPPORTED;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -950,28 +1077,44 @@ enum pm_ret_status pm_clock_setrate(unsigned int clock_id,
|
||||||
enum pm_ret_status pm_clock_getrate(unsigned int clock_id,
|
enum pm_ret_status pm_clock_getrate(unsigned int clock_id,
|
||||||
uint64_t *rate)
|
uint64_t *rate)
|
||||||
{
|
{
|
||||||
return pm_api_clock_getrate(clock_id, rate);
|
return PM_RET_ERROR_NOTSUPPORTED;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* pm_clock_setparent - Set the clock parent for given id
|
* pm_clock_setparent - Set the clock parent for given id
|
||||||
* @clock_id: Id of the clock
|
* @clock_id: Id of the clock
|
||||||
* @parent_id: parent id
|
* @parent_index: Index of the parent clock into clock's parents array
|
||||||
*
|
*
|
||||||
* This function is used by master to set parent for any clock.
|
* This function is used by master to set parent for any clock.
|
||||||
*
|
*
|
||||||
* Return: Returns status, either success or error+reason.
|
* Return: Returns status, either success or error+reason.
|
||||||
*/
|
*/
|
||||||
enum pm_ret_status pm_clock_setparent(unsigned int clock_id,
|
enum pm_ret_status pm_clock_setparent(unsigned int clock_id,
|
||||||
unsigned int parent_id)
|
unsigned int parent_index)
|
||||||
{
|
{
|
||||||
return pm_api_clock_setparent(clock_id, parent_id);
|
struct pm_pll *pll;
|
||||||
|
uint32_t payload[PAYLOAD_ARG_CNT];
|
||||||
|
enum pm_ret_status status;
|
||||||
|
|
||||||
|
/* First try to handle it as a PLL */
|
||||||
|
pll = pm_clock_get_pll_by_related_clk(clock_id);
|
||||||
|
if (pll)
|
||||||
|
return pm_clock_pll_set_parent(pll, clock_id, parent_index);
|
||||||
|
|
||||||
|
/* Check if clock ID is a valid on-chip clock */
|
||||||
|
status = pm_clock_id_is_valid(clock_id);
|
||||||
|
if (status != PM_RET_SUCCESS)
|
||||||
|
return status;
|
||||||
|
|
||||||
|
/* Send request to the PMU */
|
||||||
|
PM_PACK_PAYLOAD3(payload, PM_CLOCK_SETPARENT, clock_id, parent_index);
|
||||||
|
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* pm_clock_getparent - Get the clock parent for given id
|
* pm_clock_getparent - Get the clock parent for given id
|
||||||
* @clock_id: Id of the clock
|
* @clock_id: Id of the clock
|
||||||
* @parent_id: parent id
|
* @parent_index: parent index
|
||||||
*
|
*
|
||||||
* This function is used by master to get parent index
|
* This function is used by master to get parent index
|
||||||
* for any clock.
|
* for any clock.
|
||||||
|
@ -979,9 +1122,25 @@ enum pm_ret_status pm_clock_setparent(unsigned int clock_id,
|
||||||
* Return: Returns status, either success or error+reason.
|
* Return: Returns status, either success or error+reason.
|
||||||
*/
|
*/
|
||||||
enum pm_ret_status pm_clock_getparent(unsigned int clock_id,
|
enum pm_ret_status pm_clock_getparent(unsigned int clock_id,
|
||||||
unsigned int *parent_id)
|
unsigned int *parent_index)
|
||||||
{
|
{
|
||||||
return pm_api_clock_getparent(clock_id, parent_id);
|
struct pm_pll *pll;
|
||||||
|
uint32_t payload[PAYLOAD_ARG_CNT];
|
||||||
|
enum pm_ret_status status;
|
||||||
|
|
||||||
|
/* First try to handle it as a PLL */
|
||||||
|
pll = pm_clock_get_pll_by_related_clk(clock_id);
|
||||||
|
if (pll)
|
||||||
|
return pm_clock_pll_get_parent(pll, clock_id, parent_index);
|
||||||
|
|
||||||
|
/* Check if clock ID is a valid on-chip clock */
|
||||||
|
status = pm_clock_id_is_valid(clock_id);
|
||||||
|
if (status != PM_RET_SUCCESS)
|
||||||
|
return status;
|
||||||
|
|
||||||
|
/* Send request to the PMU */
|
||||||
|
PM_PACK_PAYLOAD2(payload, PM_CLOCK_GETPARENT, clock_id);
|
||||||
|
return pm_ipi_send_sync(primary_proc, payload, parent_index, 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1238,3 +1397,113 @@ enum pm_ret_status pm_fpga_read(uint32_t reg_numframes,
|
||||||
address_high, readback_type);
|
address_high, readback_type);
|
||||||
return pm_ipi_send_sync(primary_proc, payload, value, 1);
|
return pm_ipi_send_sync(primary_proc, payload, value, 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* pm_pll_set_parameter() - Set the PLL parameter value
|
||||||
|
* @nid Node id of the target PLL
|
||||||
|
* @param_id ID of the PLL parameter
|
||||||
|
* @value Parameter value to be set
|
||||||
|
*
|
||||||
|
* Setting the parameter will have physical effect once the PLL mode is set to
|
||||||
|
* integer or fractional.
|
||||||
|
*
|
||||||
|
* @return Error if an argument is not valid or status as returned by the
|
||||||
|
* PM controller (PMU)
|
||||||
|
*/
|
||||||
|
enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid,
|
||||||
|
enum pm_pll_param param_id,
|
||||||
|
unsigned int value)
|
||||||
|
{
|
||||||
|
uint32_t payload[PAYLOAD_ARG_CNT];
|
||||||
|
|
||||||
|
/* Check if given node ID is a PLL node */
|
||||||
|
if (nid < NODE_APLL || nid > NODE_IOPLL)
|
||||||
|
return PM_RET_ERROR_ARGS;
|
||||||
|
|
||||||
|
/* Check if parameter ID is valid and return an error if it's not */
|
||||||
|
if (param_id >= PM_PLL_PARAM_MAX)
|
||||||
|
return PM_RET_ERROR_ARGS;
|
||||||
|
|
||||||
|
/* Send request to the PMU */
|
||||||
|
PM_PACK_PAYLOAD4(payload, PM_PLL_SET_PARAMETER, nid, param_id, value);
|
||||||
|
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* pm_pll_get_parameter() - Get the PLL parameter value
|
||||||
|
* @nid Node id of the target PLL
|
||||||
|
* @param_id ID of the PLL parameter
|
||||||
|
* @value Location to store the parameter value
|
||||||
|
*
|
||||||
|
* @return Error if an argument is not valid or status as returned by the
|
||||||
|
* PM controller (PMU)
|
||||||
|
*/
|
||||||
|
enum pm_ret_status pm_pll_get_parameter(enum pm_node_id nid,
|
||||||
|
enum pm_pll_param param_id,
|
||||||
|
unsigned int *value)
|
||||||
|
{
|
||||||
|
uint32_t payload[PAYLOAD_ARG_CNT];
|
||||||
|
|
||||||
|
/* Check if given node ID is a PLL node */
|
||||||
|
if (nid < NODE_APLL || nid > NODE_IOPLL)
|
||||||
|
return PM_RET_ERROR_ARGS;
|
||||||
|
|
||||||
|
/* Check if parameter ID is valid and return an error if it's not */
|
||||||
|
if (param_id >= PM_PLL_PARAM_MAX)
|
||||||
|
return PM_RET_ERROR_ARGS;
|
||||||
|
|
||||||
|
/* Send request to the PMU */
|
||||||
|
PM_PACK_PAYLOAD3(payload, PM_PLL_GET_PARAMETER, nid, param_id);
|
||||||
|
return pm_ipi_send_sync(primary_proc, payload, value, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* pm_pll_set_mode() - Set the PLL mode
|
||||||
|
* @nid Node id of the target PLL
|
||||||
|
* @mode PLL mode to be set
|
||||||
|
*
|
||||||
|
* If reset mode is set the PM controller will first bypass the PLL and then
|
||||||
|
* assert the reset. If integer or fractional mode is set the PM controller will
|
||||||
|
* ensure that the complete PLL programming sequence is satisfied. After this
|
||||||
|
* function returns success the PLL is locked and its bypass is deasserted.
|
||||||
|
*
|
||||||
|
* @return Error if an argument is not valid or status as returned by the
|
||||||
|
* PM controller (PMU)
|
||||||
|
*/
|
||||||
|
enum pm_ret_status pm_pll_set_mode(enum pm_node_id nid, enum pm_pll_mode mode)
|
||||||
|
{
|
||||||
|
uint32_t payload[PAYLOAD_ARG_CNT];
|
||||||
|
|
||||||
|
/* Check if given node ID is a PLL node */
|
||||||
|
if (nid < NODE_APLL || nid > NODE_IOPLL)
|
||||||
|
return PM_RET_ERROR_ARGS;
|
||||||
|
|
||||||
|
/* Check if PLL mode is valid */
|
||||||
|
if (mode >= PM_PLL_MODE_MAX)
|
||||||
|
return PM_RET_ERROR_ARGS;
|
||||||
|
|
||||||
|
/* Send request to the PMU */
|
||||||
|
PM_PACK_PAYLOAD3(payload, PM_PLL_SET_MODE, nid, mode);
|
||||||
|
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* pm_pll_get_mode() - Get the PLL mode
|
||||||
|
* @nid Node id of the target PLL
|
||||||
|
* @mode Location to store the mode of the PLL
|
||||||
|
*
|
||||||
|
* @return Error if an argument is not valid or status as returned by the
|
||||||
|
* PM controller (PMU)
|
||||||
|
*/
|
||||||
|
enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode)
|
||||||
|
{
|
||||||
|
uint32_t payload[PAYLOAD_ARG_CNT];
|
||||||
|
|
||||||
|
/* Check if given node ID is a PLL node */
|
||||||
|
if (nid < NODE_APLL || nid > NODE_IOPLL)
|
||||||
|
return PM_RET_ERROR_ARGS;
|
||||||
|
|
||||||
|
/* Send request to the PMU */
|
||||||
|
PM_PACK_PAYLOAD2(payload, PM_PLL_GET_MODE, nid);
|
||||||
|
return pm_ipi_send_sync(primary_proc, payload, mode, 1);
|
||||||
|
}
|
||||||
|
|
|
@ -177,4 +177,15 @@ enum pm_ret_status pm_aes_engine(uint32_t address_high,
|
||||||
uint32_t address_low,
|
uint32_t address_low,
|
||||||
uint32_t *value);
|
uint32_t *value);
|
||||||
|
|
||||||
|
enum pm_ret_status pm_pll_set_parameter(enum pm_node_id nid,
|
||||||
|
enum pm_pll_param param_id,
|
||||||
|
unsigned int value);
|
||||||
|
|
||||||
|
enum pm_ret_status pm_pll_get_parameter(enum pm_node_id nid,
|
||||||
|
enum pm_pll_param param_id,
|
||||||
|
unsigned int *value);
|
||||||
|
|
||||||
|
enum pm_ret_status pm_pll_set_mode(enum pm_node_id nid, enum pm_pll_mode mode);
|
||||||
|
enum pm_ret_status pm_pll_get_mode(enum pm_node_id nid, enum pm_pll_mode *mode);
|
||||||
|
|
||||||
#endif /* PM_API_SYS_H */
|
#endif /* PM_API_SYS_H */
|
||||||
|
|
|
@ -92,6 +92,11 @@ enum pm_api_id {
|
||||||
/* FPGA PL Readback */
|
/* FPGA PL Readback */
|
||||||
PM_FPGA_READ,
|
PM_FPGA_READ,
|
||||||
PM_SECURE_AES,
|
PM_SECURE_AES,
|
||||||
|
/* PLL control API functions */
|
||||||
|
PM_PLL_SET_PARAMETER,
|
||||||
|
PM_PLL_GET_PARAMETER,
|
||||||
|
PM_PLL_SET_MODE,
|
||||||
|
PM_PLL_GET_MODE,
|
||||||
PM_API_MAX
|
PM_API_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -265,4 +270,51 @@ enum pm_shutdown_subtype {
|
||||||
PMF_SHUTDOWN_SUBTYPE_SYSTEM,
|
PMF_SHUTDOWN_SUBTYPE_SYSTEM,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL
|
||||||
|
* @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL
|
||||||
|
* @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL
|
||||||
|
* @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input
|
||||||
|
* @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode
|
||||||
|
* @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize
|
||||||
|
* @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting
|
||||||
|
* @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control
|
||||||
|
* @PM_PLL_PARAM_CP: PLL charge pump control
|
||||||
|
* @PM_PLL_PARAM_RES: PLL loop filter resistor control
|
||||||
|
*/
|
||||||
|
enum pm_pll_param {
|
||||||
|
PM_PLL_PARAM_DIV2,
|
||||||
|
PM_PLL_PARAM_FBDIV,
|
||||||
|
PM_PLL_PARAM_DATA,
|
||||||
|
PM_PLL_PARAM_PRE_SRC,
|
||||||
|
PM_PLL_PARAM_POST_SRC,
|
||||||
|
PM_PLL_PARAM_LOCK_DLY,
|
||||||
|
PM_PLL_PARAM_LOCK_CNT,
|
||||||
|
PM_PLL_PARAM_LFHF,
|
||||||
|
PM_PLL_PARAM_CP,
|
||||||
|
PM_PLL_PARAM_RES,
|
||||||
|
PM_PLL_PARAM_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @PM_PLL_MODE_RESET: PLL is in reset (not locked)
|
||||||
|
* @PM_PLL_MODE_INTEGER: PLL is locked in integer mode
|
||||||
|
* @PM_PLL_MODE_FRACTIONAL: PLL is locked in fractional mode
|
||||||
|
*/
|
||||||
|
enum pm_pll_mode {
|
||||||
|
PM_PLL_MODE_RESET,
|
||||||
|
PM_PLL_MODE_INTEGER,
|
||||||
|
PM_PLL_MODE_FRACTIONAL,
|
||||||
|
PM_PLL_MODE_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @PM_CLOCK_DIV0_ID: Clock divider 0
|
||||||
|
* @PM_CLOCK_DIV1_ID: Clock divider 1
|
||||||
|
*/
|
||||||
|
enum pm_clock_div_id {
|
||||||
|
PM_CLOCK_DIV0_ID,
|
||||||
|
PM_CLOCK_DIV1_ID,
|
||||||
|
};
|
||||||
|
|
||||||
#endif /* PM_DEFS_H */
|
#endif /* PM_DEFS_H */
|
||||||
|
|
|
@ -565,6 +565,30 @@ uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
|
||||||
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
case PM_PLL_SET_PARAMETER:
|
||||||
|
ret = pm_pll_set_parameter(pm_arg[0], pm_arg[1], pm_arg[2]);
|
||||||
|
SMC_RET1(handle, (uint64_t)ret);
|
||||||
|
|
||||||
|
case PM_PLL_GET_PARAMETER:
|
||||||
|
{
|
||||||
|
uint32_t value;
|
||||||
|
|
||||||
|
ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value);
|
||||||
|
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32));
|
||||||
|
}
|
||||||
|
|
||||||
|
case PM_PLL_SET_MODE:
|
||||||
|
ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]);
|
||||||
|
SMC_RET1(handle, (uint64_t)ret);
|
||||||
|
|
||||||
|
case PM_PLL_GET_MODE:
|
||||||
|
{
|
||||||
|
uint32_t mode;
|
||||||
|
|
||||||
|
ret = pm_pll_get_mode(pm_arg[0], &mode);
|
||||||
|
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32));
|
||||||
|
}
|
||||||
|
|
||||||
default:
|
default:
|
||||||
WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid);
|
WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid);
|
||||||
SMC_RET1(handle, SMC_UNK);
|
SMC_RET1(handle, SMC_UNK);
|
||||||
|
|
Loading…
Reference in New Issue