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A5DS: Change boot address to point to DDR address 

Point boot address to DDR location for booting A5DS FPGA
FIP, Kernel and rootfs are sideloaded to DDR
Also move BL2 to higher address in DDR

Change-Id: Ia2a57a0bda776a1a0a96bcd3cfb5c6cd2cf4dc04
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
This commit is contained in:
Avinash Mehta 2019-12-18 10:18:46 +00:00
parent 786890caae
commit e343bf1384
3 changed files with 26 additions and 28 deletions
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6
plat/arm/board/a5ds/a5ds_common.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -23,18 +23,18 @@
#ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
MAP_FLASH1_RW,
MAP_PERIPHBASE,
MAP_A5_PERIPHERALS,
MAP_BOOT_RW,
{0}
};
#endif
#ifdef IMAGE_BL2
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
MAP_FLASH1_RW,
MAP_PERIPHBASE,
MAP_A5_PERIPHERALS,
MAP_BOOT_RW,
ARM_MAP_NS_DRAM1,
{0}
};

4
plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, Arm Limited. All rights reserved.
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,7 +10,7 @@
/* Platform Config */
plat_arm_bl2 {
compatible = "arm,tb_fw";
hw_config_addr = <0x0 0x82000000>;
hw_config_addr = <0x0 0x83000000>;
hw_config_max_size = <0x01000000>;
/* Disable authentication for development */
disable_auth = <0x0>;

44
plat/arm/board/a5ds/include/platform_def.h
View File

@ -21,14 +21,6 @@
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1)
#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
/*
* The last 2MB is meant to be NOLOAD and will not be zero
* initialized.
*/
#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
0x00200000)
#define SRAM_BASE 0x2000000
#define SRAM_SIZE 0x200000
@ -101,17 +93,23 @@
#define A5DS_PRIMARY_CPU 0x0
#define FLASH1_BASE UL(0x8000000)
#define FLASH1_SIZE UL(0x2800000)
#define BOOT_BASE ARM_DRAM1_BASE
#define BOOT_SIZE UL(0x2800000)
#define MAP_FLASH1_RW MAP_REGION_FLAT(FLASH1_BASE,\
FLASH1_SIZE, \
#define ARM_NS_DRAM1_BASE (ARM_DRAM1_BASE + BOOT_SIZE)
/*
* The last 2MB is meant to be NOLOAD and will not be zero
* initialized.
*/
#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
BOOT_SIZE - \
0x00200000)
#define MAP_BOOT_RW MAP_REGION_FLAT( \
BOOT_BASE, \
BOOT_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
#define MAP_FLASH1_RO MAP_REGION_FLAT(FLASH1_BASE,\
FLASH1_SIZE, \
MT_RO_DATA | MT_SECURE)
#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
A5DS_SHARED_RAM_BASE, \
A5DS_SHARED_RAM_SIZE, \
@ -122,9 +120,9 @@
ARM_NS_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
#define ARM_MAP_SRAM MAP_REGION_FLAT( \
SRAM_BASE, \
SRAM_SIZE, \
#define ARM_MAP_SRAM MAP_REGION_FLAT( \
SRAM_BASE, \
SRAM_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
/*
@ -300,11 +298,11 @@
#define MAX_IO_HANDLES 4
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
#define PLAT_ARM_FIP_BASE FLASH1_BASE
#define PLAT_ARM_FIP_MAX_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
#define PLAT_ARM_FIP_BASE BOOT_BASE
#define PLAT_ARM_FIP_MAX_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
#define PLAT_ARM_NVM_BASE FLASH1_BASE
#define PLAT_ARM_NVM_SIZE (FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
#define PLAT_ARM_NVM_BASE BOOT_BASE
#define PLAT_ARM_NVM_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
/*
* PL011 related constants