Merge pull request #310 from sandrine-bailleux/sb/tf-issue-304-phase1
Enhance BL3-1 entrypoint handling to support non-TF boot firmware - Phase 1
This commit is contained in:
danh-arm
commit
e347e843a9
7
Makefile
7
Makefile
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@ -76,6 +76,9 @@ CREATE_KEYS := 1
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# Flags to build TF with Trusted Boot support
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TRUSTED_BOARD_BOOT := 0
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AUTH_MOD := none
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# By default, consider that the platform's reset address is not programmable.
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# The platform Makefile is free to override this value.
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PROGRAMMABLE_RESET_ADDRESS := 0
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# Checkpatch ignores
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CHECK_IGNORE = --ignore COMPLEX_MACRO \
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@ -272,6 +275,10 @@ $(eval $(call assert_boolean,CREATE_KEYS))
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$(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
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$(eval $(call add_define,TRUSTED_BOARD_BOOT))
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# Process PROGRAMMABLE_RESET_ADDRESS flag
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$(eval $(call assert_boolean,PROGRAMMABLE_RESET_ADDRESS))
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$(eval $(call add_define,PROGRAMMABLE_RESET_ADDRESS))
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ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \
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-Werror -Wmissing-include-dirs \
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-mgeneral-regs-only -D__ASSEMBLY__ \
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -29,7 +29,7 @@
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <el3_common_macros.S>
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.globl bl1_entrypoint
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@ -42,116 +42,19 @@
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*/
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func bl1_entrypoint
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/* ---------------------------------------------
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* Set the CPU endianness before doing anything
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* that might involve memory reads or writes.
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* ---------------------------------------------
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*/
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mrs x0, sctlr_el3
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bic x0, x0, #SCTLR_EE_BIT
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msr sctlr_el3, x0
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isb
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/* ---------------------------------------------
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* Perform any processor specific actions upon
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* reset e.g. cache, tlb invalidations etc.
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* ---------------------------------------------
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*/
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bl reset_handler
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks
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* ---------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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adr x0, bl1_exceptions
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msr vbar_el3, x0
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isb
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/* ---------------------------------------------
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* Enable the SError interrupt now that the
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* exception vectors have been setup.
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* ---------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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* (CPTR_EL3) is unknown and it must be set to a known state. All
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* feature traps are disabled. Some bits in this register are marked as
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* Reserved and should not be modified.
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*
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* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
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* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
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* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
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* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
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* access to trace functionality is not supported, this bit is RES0.
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* CPTR_EL3.TFP: This causes instructions that access the registers
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* associated with Floating Point and Advanced SIMD execution to trap
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* to EL3 when executed from any exception level, unless trapped to EL1
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* or EL2.
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* If the reset address is programmable then bl1_entrypoint() is
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* executed only on the cold boot path. Therefore, we can skip the warm
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* boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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mrs x0, cptr_el3
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bic w0, w0, #TCPAC_BIT
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bic w0, w0, #TTA_BIT
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bic w0, w0, #TFP_BIT
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msr cptr_el3, x0
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/* -------------------------------------------------------
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* Will not return from this macro if it is a warm boot.
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* -------------------------------------------------------
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*/
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wait_for_entrypoint
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bl platform_mem_init
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/* ---------------------------------------------
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* Init C runtime environment.
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* - Zero-initialise the NOBITS sections.
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* There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* - Copy the data section from BL1 image
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* (stored in ROM) to the correct location
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* in RAM.
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* ---------------------------------------------
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*/
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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#if USE_COHERENT_MEM
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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#endif
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ldr x0, =__DATA_RAM_START__
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ldr x1, =__DATA_ROM_START__
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ldr x2, =__DATA_SIZE__
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bl memcpy16
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_stack
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el3_entrypoint_common \
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_set_endian=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=1 \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl1_exceptions
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/* ---------------------------------------------
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* Architectural init. can be generic e.g.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -29,8 +29,8 @@
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <el3_common_macros.S>
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.globl bl31_entrypoint
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@ -42,154 +42,68 @@
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*/
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func bl31_entrypoint
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#if !RESET_TO_BL31
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/* ---------------------------------------------------------------
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* Preceding bootloader has populated x0 with a pointer to a
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* 'bl31_params' structure & x1 with a pointer to platform
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* specific structure
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* ---------------------------------------------------------------
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*/
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#if !RESET_TO_BL31
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mov x20, x0
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mov x21, x1
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#else
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/* ---------------------------------------------
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* Set the CPU endianness before doing anything
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* that might involve memory reads or writes.
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* ---------------------------------------------
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*/
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mrs x0, sctlr_el3
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bic x0, x0, #SCTLR_EE_BIT
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msr sctlr_el3, x0
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isb
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#endif
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/* ---------------------------------------------
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* When RESET_TO_BL31 is true, perform any
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* processor specific actions upon reset e.g.
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* cache, tlb invalidations, errata workarounds
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* etc.
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* When RESET_TO_BL31 is false, perform any
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* processor specific actions which undo or are
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* in addition to the actions performed by the
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* reset handler in the Boot ROM (BL1).
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* ---------------------------------------------
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*/
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bl reset_handler
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/* ---------------------------------------------
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* Enable the instruction cache, stack pointer
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* and data access alignment checks
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* ---------------------------------------------
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*/
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mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el3
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orr x0, x0, x1
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msr sctlr_el3, x0
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isb
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/* ---------------------------------------------
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* Initialise cpu_data early to enable crash
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* reporting to have access to crash stack.
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* Since crash reporting depends on cpu_data to
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* report the unhandled exception, not
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* doing so can lead to recursive exceptions due
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* to a NULL TPIDR_EL3
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* ---------------------------------------------
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*/
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bl init_cpu_data_ptr
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/* ---------------------------------------------
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* Set the exception vector.
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* ---------------------------------------------
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*/
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adr x1, runtime_exceptions
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msr vbar_el3, x1
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isb
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/* ---------------------------------------------
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* Enable the SError interrupt now that the
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* exception vectors have been setup.
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* ---------------------------------------------
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*/
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msr daifclr, #DAIF_ABT_BIT
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/* ---------------------------------------------------------------------
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* The initial state of the Architectural feature trap register
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* (CPTR_EL3) is unknown and it must be set to a known state. All
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* feature traps are disabled. Some bits in this register are marked as
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* Reserved and should not be modified.
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* For !RESET_TO_BL31 systems, only the primary CPU ever reaches
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* bl31_entrypoint() during the cold boot flow, so the cold/warm boot
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* and primary/secondary CPU logic should not be executed in this case.
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*
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* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
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* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
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* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
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* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
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* access to trace functionality is not supported, this bit is RES0.
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* CPTR_EL3.TFP: This causes instructions that access the registers
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* associated with Floating Point and Advanced SIMD execution to trap
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* to EL3 when executed from any exception level, unless trapped to EL1
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* or EL2.
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* Also, assume that the previous bootloader has already set up the CPU
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* endianness and has initialised the memory.
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* ---------------------------------------------------------------------
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*/
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mrs x1, cptr_el3
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bic w1, w1, #TCPAC_BIT
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bic w1, w1, #TTA_BIT
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bic w1, w1, #TFP_BIT
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msr cptr_el3, x1
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el3_entrypoint_common \
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_set_endian=0 \
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_warm_boot_mailbox=0 \
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_secondary_cold_boot=0 \
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_init_memory=0 \
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_init_c_runtime=1 \
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_exception_vectors=runtime_exceptions
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#if RESET_TO_BL31
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/* -------------------------------------------------------
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* Will not return from this macro if it is a warm boot.
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* -------------------------------------------------------
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/* ---------------------------------------------------------------------
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* Relay the previous bootloader's arguments to the platform layer
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* ---------------------------------------------------------------------
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*/
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wait_for_entrypoint
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bl platform_mem_init
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#endif
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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mov x0, x20
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mov x1, x21
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#else
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/* ---------------------------------------------------------------------
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* For RESET_TO_BL31 systems which have a programmable reset address,
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* bl31_entrypoint() is executed only on the cold boot path so we can
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* skip the warm boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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ldr x0, =__BSS_START__
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ldr x1, =__BSS_SIZE__
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bl zeromem16
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el3_entrypoint_common \
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_set_endian=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=1 \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=runtime_exceptions
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#if USE_COHERENT_MEM
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ldr x0, =__COHERENT_RAM_START__
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ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
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bl zeromem16
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#endif
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/* ---------------------------------------------
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* Use SP_EL0 for the C runtime stack.
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* ---------------------------------------------
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/* ---------------------------------------------------------------------
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* For RESET_TO_BL31 systems, BL3-1 is the first bootloader to run so
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* there's no argument to relay from a previous bootloader. Zero the
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* arguments passed to the platform layer to reflect that.
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* ---------------------------------------------------------------------
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*/
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msr spsel, #0
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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mrs x0, mpidr_el1
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bl platform_set_stack
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mov x0, 0
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mov x1, 0
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#endif /* RESET_TO_BL31 */
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/* ---------------------------------------------
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* Perform platform specific early arch. setup
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* ---------------------------------------------
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*/
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#if RESET_TO_BL31
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mov x0, 0
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mov x1, 0
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#else
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mov x0, x20
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mov x1, x21
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#endif
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bl bl31_early_platform_setup
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bl bl31_plat_arch_setup
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@ -184,7 +184,7 @@ BL1 performs minimal architectural initialization as follows.
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#### Platform initialization
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BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from
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BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
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the CCI slave interface corresponding to the cluster that includes the
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primary CPU. BL1 also initializes a UART (PL011 console), which enables access
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to the `printf` family of functions in BL1.
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@ -334,7 +334,9 @@ the clock frequency of the system counter, which is provided by the platform.
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BL3-1 performs detailed platform initialization, which enables normal world
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software to function correctly. It also retrieves entrypoint information for
|
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the BL3-3 image loaded by BL2 from the platform defined memory address populated
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by BL2. BL3-1 also initializes a UART (PL011 console), which enables
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by BL2. It enables issuing of snoop and DVM (Distributed Virtual Memory)
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requests to the CCI slave interface corresponding to the cluster that includes
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the primary CPU. BL3-1 also initializes a UART (PL011 console), which enables
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access to the `printf` family of functions in BL3-1. It enables the system
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level implementation of the generic timer through the memory mapped interface.
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@ -412,8 +414,7 @@ updated to develop and exploit new functionality.
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#### Required CPU state when calling `bl31_entrypoint()` during cold boot
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This function must only be called by the primary CPU, if this is called by any
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other CPU the firmware will abort.
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This function must only be called by the primary CPU.
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On entry to this function the calling primary CPU must be executing in AArch64
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EL3, little-endian data access, and all interrupt sources masked:
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@ -543,11 +544,6 @@ implementation via a platform defined mechanism. On a cold boot, the platform
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must place any secondary CPUs into a safe state while the primary CPU executes
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a modified BL3-1 initialization, as described below.
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#### Architectural initialization
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As the first image to execute in this configuration BL3-1 must ensure that
|
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interconnect coherency is enabled (if required) before enabling the MMU.
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#### Platform initialization
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In this configuration, when the CPU resets to BL3-1 there are no parameters
|
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@ -962,7 +958,7 @@ The sample crash output is shown below.
|
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---------------------------------
|
||||
|
||||
Trusted Firmware implements a framework that allows CPU and platform ports to
|
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perform actions immediately after a CPU is released from reset in both the cold
|
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perform actions very early after a CPU is released from reset in both the cold
|
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and warm boot paths. This is done by calling the `reset_handler()` function in
|
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both the BL1 and BL3-1 images. It in turn calls the platform and CPU specific
|
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reset handling functions.
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@ -971,33 +967,12 @@ Details for implementing a CPU specific reset handler can be found in
|
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Section 8. Details for implementing a platform specific reset handler can be
|
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found in the [Porting Guide](see the `plat_reset_handler()` function).
|
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When adding functionality to a reset handler, the following points should be
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kept in mind.
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1. The first reset handler in the system exists either in a ROM image
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(e.g. BL1), or BL3-1 if `RESET_TO_BL31` is true. This may be detected at
|
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compile time using the constant `FIRST_RESET_HANDLER_CALL`.
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2. When considering ROM images, it's important to consider non TF-based ROMs
|
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and ROMs based on previous versions of the TF code.
|
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3. If the functionality should be applied to a ROM and there is no possibility
|
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of a ROM being used that does not apply the functionality (or equivalent),
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then the functionality should be applied within a `#if
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FIRST_RESET_HANDLER_CALL` block.
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4. If the functionality should execute in BL3-1 in order to override or
|
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supplement a ROM version of the functionality, then the functionality
|
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should be applied in the `#else` part of a `#if FIRST_RESET_HANDLER_CALL`
|
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block.
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||||
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5. If the functionality should be applied to a ROM but there is a possibility
|
||||
of ROMs being used that do not apply the functionality, then the
|
||||
functionality should be applied outside of a `FIRST_RESET_HANDLER_CALL`
|
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block, so that BL3-1 has an opportunity to apply the functionality instead.
|
||||
In this case, additional code may be needed to cope with different ROMs
|
||||
that do or do not apply the functionality.
|
||||
|
||||
When adding functionality to a reset handler, keep in mind that if a different
|
||||
reset handling behavior is required between the first and the subsequent
|
||||
invocations of the reset handling code, this should be detected at runtime.
|
||||
In other words, the reset handler should be able to detect whether an action has
|
||||
already been performed and act as appropriate. Possible courses of actions are,
|
||||
e.g. skip the action the second time, or undo/redo it.
|
||||
|
||||
8. CPU specific operations framework
|
||||
-----------------------------
|
||||
|
|
|
|||
|
|
@ -434,7 +434,7 @@ This function fulfills requirement 1 and 3 listed above.
|
|||
This function is called with the MMU and data caches disabled. It is responsible
|
||||
for placing the executing secondary CPU in a platform-specific state until the
|
||||
primary CPU performs the necessary actions to bring it out of that state and
|
||||
allow entry into the OS.
|
||||
allow entry into the OS. This function must not return.
|
||||
|
||||
In the ARM FVP port, each secondary CPU powers itself off. The primary CPU is
|
||||
responsible for powering up the secondary CPU when normal world software
|
||||
|
|
@ -569,7 +569,7 @@ preserve the values of callee saved registers x19 to x29.
|
|||
|
||||
The default implementation doesn't do anything. If a platform needs to override
|
||||
the default implementation, refer to the [Firmware Design] for general
|
||||
guidelines regarding placement of code in a reset handler.
|
||||
guidelines.
|
||||
|
||||
### Function : plat_disable_acp()
|
||||
|
||||
|
|
|
|||
|
|
@ -320,6 +320,10 @@ performed.
|
|||
* `BL33_KEY`: This option is used when `GENERATE_COT=1`. It specifies the
|
||||
file that contains the BL3-3 private key in PEM format.
|
||||
|
||||
* `PROGRAMMABLE_RESET_ADDRESS`: This option indicates whether the reset
|
||||
vector address can be programmed or is fixed on the platform. It can take
|
||||
either 0 (fixed) or 1 (programmable). Default is 0.
|
||||
|
||||
#### ARM development platform specific build options
|
||||
|
||||
* `ARM_TSP_RAM_LOCATION`: location of the TSP binary. Options:
|
||||
|
|
|
|||
|
|
@ -99,41 +99,6 @@
|
|||
.size \_name, . - \_name
|
||||
.endm
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Find the type of reset and jump to handler
|
||||
* if present. If the handler is null then it is
|
||||
* a cold boot. The primary cpu will set up the
|
||||
* platform while the secondaries wait for
|
||||
* their turn to be woken up
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.macro wait_for_entrypoint
|
||||
wait_for_entrypoint:
|
||||
mrs x0, mpidr_el1
|
||||
bl platform_get_entrypoint
|
||||
cbnz x0, do_warm_boot
|
||||
mrs x0, mpidr_el1
|
||||
bl platform_is_primary_cpu
|
||||
cbnz x0, do_cold_boot
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Perform any platform specific secondary cpu
|
||||
* actions
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl plat_secondary_cold_boot_setup
|
||||
b wait_for_entrypoint
|
||||
|
||||
do_warm_boot:
|
||||
/* ---------------------------------------------
|
||||
* Jump to BL31 for all warm boot init.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
blr x0
|
||||
|
||||
do_cold_boot:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* This macro declares an array of 1 or more stacks, properly
|
||||
* aligned and in the requested section
|
||||
|
|
|
|||
|
|
@ -90,18 +90,6 @@
|
|||
(_p)->h.attr = (uint32_t)(_attr) ; \
|
||||
} while (0)
|
||||
|
||||
/*******************************************************************************
|
||||
* Constant that indicates if this is the first version of the reset handler
|
||||
* contained in an image. This will be the case when the image is BL1 or when
|
||||
* its BL3-1 and RESET_TO_BL31 is true. This constant enables a subsequent
|
||||
* version of the reset handler to perform actions that override the ones
|
||||
* performed in the first version of the code. This will be required when the
|
||||
* first version exists in an un-modifiable image e.g. a BootROM image.
|
||||
******************************************************************************/
|
||||
#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
|
||||
#define FIRST_RESET_HANDLER_CALL
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <cdefs.h> /* For __dead2 */
|
||||
#include <cassert.h>
|
||||
|
|
@ -195,9 +183,9 @@ typedef struct image_info {
|
|||
* This structure represents the superset of information that can be passed to
|
||||
* BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
|
||||
* populated only if BL2 detects its presence. A pointer to a structure of this
|
||||
* type should be passed in X3 to BL31's cold boot entrypoint
|
||||
* type should be passed in X0 to BL3-1's cold boot entrypoint.
|
||||
*
|
||||
* Use of this structure and the X3 parameter is not mandatory: the BL3-1
|
||||
* Use of this structure and the X0 parameter is not mandatory: the BL3-1
|
||||
* platform code can use other mechanisms to provide the necessary information
|
||||
* about BL3-2 and BL3-3 to the common and SPD code.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -0,0 +1,256 @@
|
|||
/*
|
||||
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __EL3_COMMON_MACROS_S__
|
||||
#define __EL3_COMMON_MACROS_S__
|
||||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
|
||||
/*
|
||||
* Helper macro to initialise EL3 registers we care about.
|
||||
*/
|
||||
.macro el3_arch_init_common _exception_vectors
|
||||
/* ---------------------------------------------------------------------
|
||||
* Enable the instruction cache, stack pointer and data access alignment
|
||||
* checks
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
|
||||
mrs x0, sctlr_el3
|
||||
orr x0, x0, x1
|
||||
msr sctlr_el3, x0
|
||||
isb
|
||||
|
||||
#if IMAGE_BL31
|
||||
/* ---------------------------------------------------------------------
|
||||
* Initialise the per-cpu cache pointer to the CPU.
|
||||
* This is done early to enable crash reporting to have access to crash
|
||||
* stack. Since crash reporting depends on cpu_data to report the
|
||||
* unhandled exception, not doing so can lead to recursive exceptions
|
||||
* due to a NULL TPIDR_EL3.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
bl init_cpu_data_ptr
|
||||
#endif /* IMAGE_BL31 */
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* Set the exception vectors.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
adr x0, \_exception_vectors
|
||||
msr vbar_el3, x0
|
||||
isb
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* Enable the SError interrupt now that the exception vectors have been
|
||||
* setup.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
msr daifclr, #DAIF_ABT_BIT
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* The initial state of the Architectural feature trap register
|
||||
* (CPTR_EL3) is unknown and it must be set to a known state. All
|
||||
* feature traps are disabled. Some bits in this register are marked as
|
||||
* reserved and should not be modified.
|
||||
*
|
||||
* CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
|
||||
* or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
|
||||
*
|
||||
* CPTR_EL3.TTA: This causes access to the Trace functionality to trap
|
||||
* to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
|
||||
* access to trace functionality is not supported, this bit is RES0.
|
||||
*
|
||||
* CPTR_EL3.TFP: This causes instructions that access the registers
|
||||
* associated with Floating Point and Advanced SIMD execution to trap
|
||||
* to EL3 when executed from any exception level, unless trapped to EL1
|
||||
* or EL2.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
mrs x0, cptr_el3
|
||||
bic w0, w0, #TCPAC_BIT
|
||||
bic w0, w0, #TTA_BIT
|
||||
bic w0, w0, #TFP_BIT
|
||||
msr cptr_el3, x0
|
||||
.endm
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* This is the super set of actions that need to be performed during a cold boot
|
||||
* or a warm boot in EL3. This code is shared by BL1 and BL3-1.
|
||||
*
|
||||
* This macro will always perform reset handling, architectural initialisations
|
||||
* and stack setup. The rest of the actions are optional because they might not
|
||||
* be needed, depending on the context in which this macro is called. This is
|
||||
* why this macro is parameterised ; each parameter allows to enable/disable
|
||||
* some actions.
|
||||
*
|
||||
* _set_endian:
|
||||
* Whether the macro needs to configure the endianness of data accesses.
|
||||
*
|
||||
* _warm_boot_mailbox:
|
||||
* Whether the macro needs to detect the type of boot (cold/warm). The
|
||||
* detection is based on the platform entrypoint address : if it is zero
|
||||
* then it is a cold boot, otherwise it is a warm boot. In the latter case,
|
||||
* this macro jumps on the platform entrypoint address.
|
||||
*
|
||||
* _secondary_cold_boot:
|
||||
* Whether the macro needs to identify the CPU that is calling it: primary
|
||||
* CPU or secondary CPU. The primary CPU will be allowed to carry on with
|
||||
* the platform initialisations, while the secondaries will be put in a
|
||||
* platform-specific state in the meantime.
|
||||
*
|
||||
* If the caller knows this macro will only be called by the primary CPU
|
||||
* then this parameter can be defined to 0 to skip this step.
|
||||
*
|
||||
* _init_memory:
|
||||
* Whether the macro needs to initialise the memory.
|
||||
*
|
||||
* _init_c_runtime:
|
||||
* Whether the macro needs to initialise the C runtime environment.
|
||||
*
|
||||
* _exception_vectors:
|
||||
* Address of the exception vectors to program in the VBAR_EL3 register.
|
||||
* -----------------------------------------------------------------------------
|
||||
*/
|
||||
.macro el3_entrypoint_common \
|
||||
_set_endian, _warm_boot_mailbox, _secondary_cold_boot, \
|
||||
_init_memory, _init_c_runtime, _exception_vectors
|
||||
|
||||
.if \_set_endian
|
||||
/* -------------------------------------------------------------
|
||||
* Set the CPU endianness before doing anything that might
|
||||
* involve memory reads or writes.
|
||||
* -------------------------------------------------------------
|
||||
*/
|
||||
mrs x0, sctlr_el3
|
||||
bic x0, x0, #SCTLR_EE_BIT
|
||||
msr sctlr_el3, x0
|
||||
isb
|
||||
.endif /* _set_endian */
|
||||
|
||||
.if \_warm_boot_mailbox
|
||||
/* -------------------------------------------------------------
|
||||
* This code will be executed for both warm and cold resets.
|
||||
* Now is the time to distinguish between the two.
|
||||
* Query the platform entrypoint address and if it is not zero
|
||||
* then it means it is a warm boot so jump to this address.
|
||||
* -------------------------------------------------------------
|
||||
*/
|
||||
mrs x0, mpidr_el1
|
||||
bl platform_get_entrypoint
|
||||
cbz x0, do_cold_boot
|
||||
br x0
|
||||
|
||||
do_cold_boot:
|
||||
.endif /* _warm_boot_mailbox */
|
||||
|
||||
.if \_secondary_cold_boot
|
||||
/* -------------------------------------------------------------
|
||||
* It is a cold boot.
|
||||
* The primary CPU will set up the platform while the
|
||||
* secondaries are placed in a platform-specific state until the
|
||||
* primary CPU performs the necessary actions to bring them out
|
||||
* of that state and allows entry into the OS.
|
||||
* -------------------------------------------------------------
|
||||
*/
|
||||
mrs x0, mpidr_el1
|
||||
bl platform_is_primary_cpu
|
||||
cbnz x0, do_primary_cold_boot
|
||||
|
||||
/* This is a cold boot on a secondary CPU */
|
||||
bl plat_secondary_cold_boot_setup
|
||||
/* plat_secondary_cold_boot_setup() is not supposed to return */
|
||||
secondary_panic:
|
||||
b secondary_panic
|
||||
|
||||
do_primary_cold_boot:
|
||||
.endif /* _secondary_cold_boot */
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* Perform any processor specific actions upon reset e.g. cache, TLB
|
||||
* invalidations etc.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
bl reset_handler
|
||||
|
||||
el3_arch_init_common \_exception_vectors
|
||||
|
||||
.if \_init_memory
|
||||
bl platform_mem_init
|
||||
.endif /* _init_memory */
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* Init C runtime environment:
|
||||
* - Zero-initialise the NOBITS sections. There are 2 of them:
|
||||
* - the .bss section;
|
||||
* - the coherent memory section (if any).
|
||||
* - Relocate the data section from ROM to RAM, if required.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
.if \_init_c_runtime
|
||||
ldr x0, =__BSS_START__
|
||||
ldr x1, =__BSS_SIZE__
|
||||
bl zeromem16
|
||||
|
||||
#if USE_COHERENT_MEM
|
||||
ldr x0, =__COHERENT_RAM_START__
|
||||
ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
|
||||
bl zeromem16
|
||||
#endif
|
||||
|
||||
#ifdef __DATA_ROM_START__
|
||||
ldr x0, =__DATA_RAM_START__
|
||||
ldr x1, =__DATA_ROM_START__
|
||||
ldr x2, =__DATA_SIZE__
|
||||
bl memcpy16
|
||||
#endif
|
||||
.endif /* _init_c_runtime */
|
||||
|
||||
#if IMAGE_BL31
|
||||
/* ---------------------------------------------------------------------
|
||||
* Use SP_EL0 for the C runtime stack.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
msr spsel, #0
|
||||
#endif /* IMAGE_BL31 */
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* Allocate a stack whose memory will be marked as Normal-IS-WBWA when
|
||||
* the MMU is enabled. There is no risk of reading stale stack memory
|
||||
* after enabling the MMU as only the primary CPU is running at the
|
||||
* moment.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
mrs x0, mpidr_el1
|
||||
bl platform_set_stack
|
||||
.endm
|
||||
|
||||
#endif /* __EL3_COMMON_MACROS_S__ */
|
||||
|
|
@ -45,13 +45,13 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
|
|||
* No need for locks as no other CPU is active.
|
||||
*/
|
||||
fvp_cci_init();
|
||||
#if RESET_TO_BL31
|
||||
|
||||
/*
|
||||
* Enable CCI coherency for the primary CPU's cluster
|
||||
* (if earlier BL has not already done so).
|
||||
* Enable CCI coherency for the primary CPU's cluster.
|
||||
* Earlier bootloader stages might already do this (e.g. Trusted
|
||||
* Firmware's BL1 does it) but we can't assume so. There is no harm in
|
||||
* executing this code twice anyway.
|
||||
* FVP PSCI code will enable coherency for other clusters.
|
||||
*/
|
||||
fvp_cci_enable();
|
||||
|
||||
#endif /* RESET_TO_BL31 */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,10 +42,6 @@
|
|||
/* --------------------------------------------------------------------
|
||||
* void plat_reset_handler(void);
|
||||
*
|
||||
* Before adding code in this function, refer to the guidelines in
|
||||
* docs/firmware-design.md to determine whether the code should reside
|
||||
* within the FIRST_RESET_HANDLER_CALL block or not.
|
||||
*
|
||||
* For Juno r0:
|
||||
* - Implement workaround for defect id 831273 by enabling an event
|
||||
* stream every 65536 cycles.
|
||||
|
|
@ -58,13 +54,9 @@
|
|||
* - The default value for the L2 Tag RAM latency for Cortex-A57 is
|
||||
* suitable.
|
||||
* - Defect #831273 doesn't affect Juno r1.
|
||||
*
|
||||
* This code is included only when FIRST_RESET_HANDLER_CALL is defined
|
||||
* since it should be executed only during BL1.
|
||||
* --------------------------------------------------------------------
|
||||
*/
|
||||
func plat_reset_handler
|
||||
#ifdef FIRST_RESET_HANDLER_CALL
|
||||
/* --------------------------------------------------------------------
|
||||
* Determine whether this code is running on Juno r0 or Juno r1.
|
||||
* Keep this information in x2.
|
||||
|
|
@ -123,6 +115,5 @@ apply_831273:
|
|||
msr CNTKCTL_EL1, x0
|
||||
ret:
|
||||
isb
|
||||
#endif /* FIRST_RESET_HANDLER_CALL */
|
||||
ret
|
||||
endfunc plat_reset_handler
|
||||
|
|
|
|||
|
|
@ -179,16 +179,16 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
|
|||
* No need for locks as no other CPU is active.
|
||||
*/
|
||||
arm_cci_init();
|
||||
#if RESET_TO_BL31
|
||||
|
||||
/*
|
||||
* Enable CCI coherency for the primary CPU's cluster
|
||||
* (if earlier BL has not already done so).
|
||||
* Enable CCI coherency for the primary CPU's cluster.
|
||||
* Earlier bootloader stages might already do this (e.g. Trusted
|
||||
* Firmware's BL1 does it) but we can't assume so. There is no harm in
|
||||
* executing this code twice anyway.
|
||||
* Platform specific PSCI code will enable coherency for other
|
||||
* clusters.
|
||||
*/
|
||||
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
|
||||
|
||||
#endif /* RESET_TO_BL31 */
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
|
|
@ -30,6 +30,7 @@
|
|||
|
||||
#include <arch.h>
|
||||
#include <asm_macros.S>
|
||||
#include <el3_common_macros.S>
|
||||
#include <psci.h>
|
||||
#include <xlat_tables.h>
|
||||
|
||||
|
|
@ -52,69 +53,30 @@ psci_aff_suspend_finish_entry:
|
|||
adr x23, psci_afflvl_suspend_finishers
|
||||
|
||||
psci_aff_common_finish_entry:
|
||||
#if !RESET_TO_BL31
|
||||
/* ---------------------------------------------
|
||||
* Perform any processor specific actions which
|
||||
* undo or are in addition to the actions
|
||||
* performed by the reset handler in the BootROM
|
||||
* (BL1) e.g. cache, tlb invalidations, errata
|
||||
* workarounds etc.
|
||||
* ---------------------------------------------
|
||||
/*
|
||||
* On the warm boot path, most of the EL3 initialisations performed by
|
||||
* 'el3_entrypoint_common' must be skipped:
|
||||
*
|
||||
* - Only when the platform bypasses the BL1/BL3-1 entrypoint by
|
||||
* programming the reset address do we need to set the CPU endianness.
|
||||
* In other cases, we assume this has been taken care by the
|
||||
* entrypoint code.
|
||||
*
|
||||
* - No need to determine the type of boot, we know it is a warm boot.
|
||||
*
|
||||
* - Do not try to distinguish between primary and secondary CPUs, this
|
||||
* notion only exists for a cold boot.
|
||||
*
|
||||
* - No need to initialise the memory or the C runtime environment,
|
||||
* it has been done once and for all on the cold boot path.
|
||||
*/
|
||||
bl reset_handler
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Enable the instruction cache, stack pointer
|
||||
* and data access alignment checks.
|
||||
* It can be assumed that BL3-1 entrypoint code
|
||||
* will do this when RESET_TO_BL31 is set. The
|
||||
* same assumption cannot be made when another
|
||||
* boot loader executes before BL3-1 in the warm
|
||||
* boot path e.g. BL1.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
|
||||
mrs x0, sctlr_el3
|
||||
orr x0, x0, x1
|
||||
msr sctlr_el3, x0
|
||||
isb
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Initialise the pcpu cache pointer for the CPU
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
bl init_cpu_data_ptr
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Set the exception vectors
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
adr x0, runtime_exceptions
|
||||
msr vbar_el3, x0
|
||||
isb
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Enable the SError interrupt now that the
|
||||
* exception vectors have been setup.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
msr daifclr, #DAIF_ABT_BIT
|
||||
|
||||
/* ---------------------------------------------
|
||||
* Use SP_EL0 for the C runtime stack.
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
msr spsel, #0
|
||||
|
||||
/* --------------------------------------------
|
||||
* Give ourselves a stack whose memory will be
|
||||
* marked as Normal-IS-WBWA when the MMU is
|
||||
* enabled.
|
||||
* --------------------------------------------
|
||||
*/
|
||||
mrs x0, mpidr_el1
|
||||
bl platform_set_stack
|
||||
el3_entrypoint_common \
|
||||
_set_endian=PROGRAMMABLE_RESET_ADDRESS \
|
||||
_warm_boot_mailbox=0 \
|
||||
_secondary_cold_boot=0 \
|
||||
_init_memory=0 \
|
||||
_init_c_runtime=0 \
|
||||
_exception_vectors=runtime_exceptions
|
||||
|
||||
/* --------------------------------------------
|
||||
* Enable the MMU with the DCache disabled. It
|
||||
|
|
|
|||
Loading…
Reference in New Issue