drivers: Add iproc spi driver
Add iproc spi driver Change-Id: I652efab1efd9c487974dae9cb9d98b9b8e3759c4 Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
This commit is contained in:
Sheetal Tigadoli
parent
bffde63de7
commit
e3ee7b7dc8
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/*
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* Copyright (c) 2017 - 2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <string.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <endian.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <spi.h>
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#include "iproc_qspi.h"
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struct bcmspi_priv spi_cfg;
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/* Redefined by platform to force appropriate information */
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#pragma weak plat_spi_init
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int plat_spi_init(uint32_t *max_hz)
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{
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return 0;
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}
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/* Initialize & setup iproc qspi controller */
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int iproc_qspi_setup(uint32_t bus, uint32_t cs, uint32_t max_hz, uint32_t mode)
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{
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struct bcmspi_priv *priv = NULL;
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uint32_t spbr;
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priv = &spi_cfg;
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priv->spi_mode = mode;
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priv->state = QSPI_STATE_DISABLED;
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priv->bspi_hw = QSPI_BSPI_MODE_REG_BASE;
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priv->mspi_hw = QSPI_MSPI_MODE_REG_BASE;
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/* Initialize clock and platform specific */
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if (plat_spi_init(&max_hz) != 0)
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return -1;
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priv->max_hz = max_hz;
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/* MSPI: Basic hardware initialization */
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mmio_write_32(priv->mspi_hw + MSPI_SPCR1_LSB_REG, 0);
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mmio_write_32(priv->mspi_hw + MSPI_SPCR1_MSB_REG, 0);
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mmio_write_32(priv->mspi_hw + MSPI_NEWQP_REG, 0);
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mmio_write_32(priv->mspi_hw + MSPI_ENDQP_REG, 0);
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mmio_write_32(priv->mspi_hw + MSPI_SPCR2_REG, 0);
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/* MSPI: SCK configuration */
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spbr = (QSPI_AXI_CLK - 1) / (2 * priv->max_hz) + 1;
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spbr = MIN(spbr, SPBR_DIV_MAX);
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spbr = MAX(spbr, SPBR_DIV_MIN);
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mmio_write_32(priv->mspi_hw + MSPI_SPCR0_LSB_REG, spbr);
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/* MSPI: Mode configuration (8 bits by default) */
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priv->mspi_16bit = 0;
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mmio_write_32(priv->mspi_hw + MSPI_SPCR0_MSB_REG,
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BIT(MSPI_SPCR0_MSB_REG_MSTR_SHIFT) | /* Master */
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MSPI_SPCR0_MSB_REG_16_BITS_PER_WD_SHIFT | /* 16 bits per word */
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(priv->spi_mode & MSPI_SPCR0_MSB_REG_MODE_MASK)); /* mode: CPOL / CPHA */
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/* Display bus info */
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VERBOSE("SPI: SPCR0_LSB: 0x%x\n",
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mmio_read_32(priv->mspi_hw + MSPI_SPCR0_LSB_REG));
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VERBOSE("SPI: SPCR0_MSB: 0x%x\n",
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mmio_read_32(priv->mspi_hw + MSPI_SPCR0_MSB_REG));
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VERBOSE("SPI: SPCR1_LSB: 0x%x\n",
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mmio_read_32(priv->mspi_hw + MSPI_SPCR1_LSB_REG));
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VERBOSE("SPI: SPCR1_MSB: 0x%x\n",
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mmio_read_32(priv->mspi_hw + MSPI_SPCR1_MSB_REG));
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VERBOSE("SPI: SPCR2: 0x%x\n",
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mmio_read_32(priv->mspi_hw + MSPI_SPCR2_REG));
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VERBOSE("SPI: CLK: %d\n", priv->max_hz);
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return 0;
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}
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void bcmspi_enable_bspi(struct bcmspi_priv *priv)
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{
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if (priv->state != QSPI_STATE_BSPI) {
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/* Switch to BSPI */
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mmio_write_32(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG, 0);
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priv->state = QSPI_STATE_BSPI;
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}
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}
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static int bcmspi_disable_bspi(struct bcmspi_priv *priv)
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{
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uint32_t retry;
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if (priv->state == QSPI_STATE_MSPI)
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return 0;
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/* Switch to MSPI if not yet */
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if ((mmio_read_32(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG) &
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MSPI_CTRL_MASK) == 0) {
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retry = QSPI_RETRY_COUNT_US_MAX;
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do {
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if ((mmio_read_32(
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priv->bspi_hw + BSPI_BUSY_STATUS_REG) &
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BSPI_BUSY_MASK) == 0) {
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mmio_write_32(priv->bspi_hw +
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BSPI_MAST_N_BOOT_CTRL_REG,
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MSPI_CTRL_MASK);
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udelay(1);
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break;
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}
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udelay(1);
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} while (retry--);
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if ((mmio_read_32(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG) &
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MSPI_CTRL_MASK) != MSPI_CTRL_MASK) {
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ERROR("QSPI: Switching to QSPI error.\n");
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return -1;
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}
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}
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/* Update state */
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priv->state = QSPI_STATE_MSPI;
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return 0;
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}
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int iproc_qspi_claim_bus(void)
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{
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struct bcmspi_priv *priv = &spi_cfg;
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/* Switch to MSPI by default */
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if (bcmspi_disable_bspi(priv) != 0)
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return -1;
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return 0;
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}
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void iproc_qspi_release_bus(void)
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{
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struct bcmspi_priv *priv = &spi_cfg;
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/* Switch to BSPI by default */
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bcmspi_enable_bspi(priv);
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}
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static int mspi_xfer(struct bcmspi_priv *priv, uint32_t bytes,
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const uint8_t *tx, uint8_t *rx, uint32_t flag)
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{
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uint32_t retry;
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uint32_t mode = CDRAM_PCS0;
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if (flag & SPI_XFER_QUAD) {
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mode |= CDRAM_QUAD_MODE;
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VERBOSE("SPI: QUAD mode\n");
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if (!tx) {
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VERBOSE("SPI: 4 lane input\n");
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mode |= CDRAM_RBIT_INPUT;
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}
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}
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/* Use 8-bit queue for odd-bytes transfer */
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if (bytes & 1)
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priv->mspi_16bit = 0;
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else {
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priv->mspi_16bit = 1;
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mode |= CDRAM_BITS_EN;
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}
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while (bytes) {
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uint32_t chunk;
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uint32_t queues;
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uint32_t i;
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/* Separate code for 16bit and 8bit transfers for performance */
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if (priv->mspi_16bit) {
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VERBOSE("SPI: 16 bits xfer\n");
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/* Determine how many bytes to process this time */
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chunk = MIN(bytes, NUM_CDRAM_BYTES * 2);
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queues = (chunk - 1) / 2 + 1;
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bytes -= chunk;
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/* Fill CDRAMs */
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for (i = 0; i < queues; i++)
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mmio_write_32(priv->mspi_hw + MSPI_CDRAM_REG +
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(i << 2), mode | CDRAM_CONT);
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/* Fill TXRAMs */
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for (i = 0; i < chunk; i++)
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if (tx)
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mmio_write_32(priv->mspi_hw +
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MSPI_TXRAM_REG +
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(i << 2), tx[i]);
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} else {
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VERBOSE("SPI: 8 bits xfer\n");
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/* Determine how many bytes to process this time */
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chunk = MIN(bytes, NUM_CDRAM_BYTES);
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queues = chunk;
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bytes -= chunk;
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/* Fill CDRAMs and TXRAMS */
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for (i = 0; i < chunk; i++) {
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mmio_write_32(priv->mspi_hw + MSPI_CDRAM_REG +
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(i << 2), mode | CDRAM_CONT);
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if (tx)
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mmio_write_32(priv->mspi_hw +
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MSPI_TXRAM_REG +
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(i << 3), tx[i]);
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}
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}
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/* Advance pointers */
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if (tx)
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tx += chunk;
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/* Setup queue pointers */
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mmio_write_32(priv->mspi_hw + MSPI_NEWQP_REG, 0);
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mmio_write_32(priv->mspi_hw + MSPI_ENDQP_REG, queues - 1);
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/* Remove CONT on the last byte command */
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if (bytes == 0 && (flag & SPI_XFER_END))
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mmio_write_32(priv->mspi_hw + MSPI_CDRAM_REG +
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((queues - 1) << 2), mode);
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/* Kick off */
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mmio_write_32(priv->mspi_hw + MSPI_STATUS_REG, 0);
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if (bytes == 0 && (flag & SPI_XFER_END))
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mmio_write_32(priv->mspi_hw + MSPI_SPCR2_REG, MSPI_SPE);
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else
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mmio_write_32(priv->mspi_hw + MSPI_SPCR2_REG,
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MSPI_SPE | MSPI_CONT_AFTER_CMD);
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/* Wait for completion */
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retry = QSPI_RETRY_COUNT_US_MAX;
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do {
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if (mmio_read_32(priv->mspi_hw + MSPI_STATUS_REG) &
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MSPI_CMD_COMPLETE_MASK)
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break;
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udelay(1);
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} while (retry--);
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if ((mmio_read_32(priv->mspi_hw + MSPI_STATUS_REG) &
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MSPI_CMD_COMPLETE_MASK) == 0) {
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ERROR("SPI: Completion timeout.\n");
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return -1;
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}
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/* Read data out */
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if (rx) {
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if (priv->mspi_16bit) {
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for (i = 0; i < chunk; i++) {
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rx[i] = mmio_read_32(priv->mspi_hw +
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MSPI_RXRAM_REG +
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(i << 2))
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& 0xff;
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}
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} else {
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for (i = 0; i < chunk; i++) {
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rx[i] = mmio_read_32(priv->mspi_hw +
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MSPI_RXRAM_REG +
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(((i << 1) + 1) << 2))
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& 0xff;
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}
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}
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rx += chunk;
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}
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}
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return 0;
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}
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int iproc_qspi_xfer(uint32_t bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct bcmspi_priv *priv;
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const uint8_t *tx = dout;
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uint8_t *rx = din;
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uint32_t bytes = bitlen / 8;
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int ret = 0;
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priv = &spi_cfg;
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if (priv->state == QSPI_STATE_DISABLED) {
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ERROR("QSPI: state disabled\n");
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return -1;
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}
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/* we can only do 8 bit transfers */
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if (bitlen % 8) {
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ERROR("QSPI: Only support 8 bit transfers (requested %d)\n",
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bitlen);
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return -1;
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}
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/* MSPI: Enable write lock at the beginning */
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if (flags & SPI_XFER_BEGIN) {
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/* Switch to MSPI if not yet */
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if (bcmspi_disable_bspi(priv) != 0) {
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ERROR("QSPI: Switch to MSPI failed\n");
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return -1;
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}
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mmio_write_32(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 1);
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}
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/* MSPI: Transfer it */
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if (bytes)
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ret = mspi_xfer(priv, bytes, tx, rx, flags);
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/* MSPI: Disable write lock if it's done */
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if (flags & SPI_XFER_END)
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mmio_write_32(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 0);
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return ret;
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}
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@ -0,0 +1,107 @@
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/*
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* Copyright (c) 2017 - 2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef IPROC_QSPI_H
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#define IPROC_QSPI_H
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#include <platform_def.h>
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/*SPI configuration enable*/
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#define IPROC_QSPI_CLK_SPEED 62500000
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#define SPI_CPHA (1 << 0)
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#define SPI_CPOL (1 << 1)
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#define IPROC_QSPI_MODE0 0
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#define IPROC_QSPI_MODE3 (SPI_CPOL|SPI_CPHA)
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#define IPROC_QSPI_BUS 0
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#define IPROC_QSPI_CS 0
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#define IPROC_QSPI_BASE_REG QSPI_CTRL_BASE_ADDR
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#define IPROC_QSPI_CRU_CONTROL_REG QSPI_CLK_CTRL
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#define QSPI_AXI_CLK 200000000
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#define QSPI_RETRY_COUNT_US_MAX 200000
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/* Chip attributes */
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#define QSPI_REG_BASE IPROC_QSPI_BASE_REG
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#define CRU_CONTROL_REG IPROC_QSPI_CRU_CONTROL_REG
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#define SPBR_DIV_MIN 8U
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#define SPBR_DIV_MAX 255U
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#define NUM_CDRAM_BYTES 16U
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/* Register fields */
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#define MSPI_SPCR0_MSB_BITS_8 0x00000020
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/* Flash opcode and parameters */
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#define CDRAM_PCS0 2
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#define CDRAM_CONT (1 << 7)
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#define CDRAM_BITS_EN (1 << 6)
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#define CDRAM_QUAD_MODE (1 << 8)
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#define CDRAM_RBIT_INPUT (1 << 10)
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/* MSPI registers */
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#define QSPI_MSPI_MODE_REG_BASE (QSPI_REG_BASE + 0x200)
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#define MSPI_SPCR0_LSB_REG 0x000
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#define MSPI_SPCR0_MSB_REG 0x004
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#define MSPI_SPCR1_LSB_REG 0x008
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#define MSPI_SPCR1_MSB_REG 0x00c
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#define MSPI_NEWQP_REG 0x010
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#define MSPI_ENDQP_REG 0x014
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#define MSPI_SPCR2_REG 0x018
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#define MSPI_STATUS_REG 0x020
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#define MSPI_CPTQP_REG 0x024
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#define MSPI_TXRAM_REG 0x040
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#define MSPI_RXRAM_REG 0x0c0
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#define MSPI_CDRAM_REG 0x140
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#define MSPI_WRITE_LOCK_REG 0x180
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#define MSPI_DISABLE_FLUSH_GEN_REG 0x184
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#define MSPI_SPCR0_MSB_REG_MSTR_SHIFT 7
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#define MSPI_SPCR0_MSB_REG_16_BITS_PER_WD_SHIFT (0 << 2)
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#define MSPI_SPCR0_MSB_REG_MODE_MASK 0x3
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/* BSPI registers */
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#define QSPI_BSPI_MODE_REG_BASE QSPI_REG_BASE
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#define BSPI_MAST_N_BOOT_CTRL_REG 0x008
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#define BSPI_BUSY_STATUS_REG 0x00c
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#define MSPI_CMD_COMPLETE_MASK 1
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#define BSPI_BUSY_MASK 1
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#define MSPI_CTRL_MASK 1
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#define MSPI_SPE (1 << 6)
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#define MSPI_CONT_AFTER_CMD (1 << 7)
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/* State */
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enum bcm_qspi_state {
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QSPI_STATE_DISABLED,
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QSPI_STATE_MSPI,
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QSPI_STATE_BSPI
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};
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/* QSPI private data */
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struct bcmspi_priv {
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/* Specified SPI parameters */
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uint32_t max_hz;
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uint32_t spi_mode;
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/* State */
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enum bcm_qspi_state state;
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int mspi_16bit;
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/* Registers */
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uintptr_t mspi_hw;
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uintptr_t bspi_hw;
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};
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int iproc_qspi_setup(uint32_t bus, uint32_t cs,
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uint32_t max_hz, uint32_t mode);
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int iproc_qspi_claim_bus(void);
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void iproc_qspi_release_bus(void);
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int iproc_qspi_xfer(uint32_t bitlen, const void *dout,
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void *din, unsigned long flags);
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#endif /* _IPROC_QSPI_H_ */
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@ -0,0 +1,31 @@
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/*
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* Copyright (c) 2017 - 2020, Broadcom
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <spi.h>
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#include "iproc_qspi.h"
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int spi_init(void)
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{
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return iproc_qspi_setup(IPROC_QSPI_BUS, IPROC_QSPI_CS,
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IPROC_QSPI_CLK_SPEED, IPROC_QSPI_MODE0);
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}
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int spi_claim_bus(void)
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{
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return iproc_qspi_claim_bus();
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}
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void spi_release_bus(void)
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{
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iproc_qspi_release_bus();
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}
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int spi_xfer(uint32_t bitlen, const void *dout,
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void *din, uint32_t flags)
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{
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return iproc_qspi_xfer(bitlen, dout, din, flags);
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}
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2017 - 2020, Broadcom
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef SPI_H
|
||||
#define SPI_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define SPI_XFER_BEGIN (1 << 0) /* Assert CS before transfer */
|
||||
#define SPI_XFER_END (1 << 1) /* De-assert CS after transfer */
|
||||
#define SPI_XFER_QUAD (1 << 2)
|
||||
|
||||
int spi_init(void);
|
||||
int spi_claim_bus(void);
|
||||
void spi_release_bus(void);
|
||||
int spi_xfer(uint32_t bitlen, const void *dout, void *din, uint32_t flags);
|
||||
|
||||
#endif /* _SPI_H_ */
|
||||
|
|
@ -32,6 +32,10 @@ ifeq (${DRIVER_EMMC_ENABLE},)
|
|||
DRIVER_EMMC_ENABLE :=1
|
||||
endif
|
||||
|
||||
ifeq (${DRIVER_SPI_ENABLE},)
|
||||
DRIVER_SPI_ENABLE := 0
|
||||
endif
|
||||
|
||||
# By default, Trusted Watchdog is always enabled unless SPIN_ON_BL1_EXIT is set
|
||||
ifeq (${BRCM_DISABLE_TRUSTED_WDOG},)
|
||||
BRCM_DISABLE_TRUSTED_WDOG := 0
|
||||
|
|
@ -159,6 +163,12 @@ BL2_SOURCES += ${ELOG_SOURCES}
|
|||
BL31_SOURCES += ${ELOG_SOURCES}
|
||||
endif
|
||||
|
||||
# Add spi driver
|
||||
ifeq (${DRIVER_SPI_ENABLE},1)
|
||||
PLAT_BL_COMMON_SOURCES += drivers/brcm/spi/iproc_spi.c \
|
||||
drivers/brcm/spi/iproc_qspi.c
|
||||
endif
|
||||
|
||||
ifeq (${DRIVER_OCOTP_ENABLE},1)
|
||||
$(eval $(call add_define,DRIVER_OCOTP_ENABLE))
|
||||
BL2_SOURCES += drivers/brcm/ocotp.c
|
||||
|
|
|
|||
|
|
@ -172,6 +172,10 @@ $(eval $(call add_define,CONFIG_SOFT_RESET_L3))
|
|||
# Enable Chip OTP driver
|
||||
DRIVER_OCOTP_ENABLE := 1
|
||||
|
||||
ifneq (${WARMBOOT_DDR_S3_SUPPORT},)
|
||||
DRIVER_SPI_ENABLE := 1
|
||||
endif
|
||||
|
||||
include plat/brcm/board/common/board_common.mk
|
||||
|
||||
SOC_DIR := brcm/board/stingray
|
||||
|
|
|
|||
Loading…
Reference in New Issue