Tegra: remove weakly defined PSCI platform handlers
This patch removes all the weakly defined PSCI handlers defined per-platform, to improve code coverage numbers and reduce MISRA defects. Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
parent
39171cd033
commit
e44f86ef2b
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -27,97 +28,6 @@
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extern uint64_t tegra_bl31_phys_base;
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extern uint64_t tegra_bl31_phys_base;
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extern uint64_t tegra_sec_entry_point;
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extern uint64_t tegra_sec_entry_point;
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/*
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* The following platform setup functions are weakly defined. They
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* provide typical implementations that will be overridden by a SoC.
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*/
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#pragma weak tegra_soc_pwr_domain_suspend_pwrdown_early
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#pragma weak tegra_soc_cpu_standby
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#pragma weak tegra_soc_pwr_domain_suspend
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#pragma weak tegra_soc_pwr_domain_on
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#pragma weak tegra_soc_pwr_domain_off
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#pragma weak tegra_soc_pwr_domain_on_finish
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#pragma weak tegra_soc_pwr_domain_power_down_wfi
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#pragma weak tegra_soc_prepare_system_reset
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#pragma weak tegra_soc_prepare_system_off
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#pragma weak tegra_soc_get_target_pwr_state
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int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
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{
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(void)cpu_state;
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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(void)target_state;
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return PSCI_E_NOT_SUPPORTED;
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}
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int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
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{
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(void)mpidr;
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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{
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(void)target_state;
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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(void)target_state;
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
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{
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(void)target_state;
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_prepare_system_reset(void)
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{
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return PSCI_E_SUCCESS;
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}
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__dead2 void tegra_soc_prepare_system_off(void)
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{
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ERROR("Tegra System Off: operation not handled.\n");
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panic();
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}
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plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
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const plat_local_state_t *states,
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uint32_t ncpu)
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{
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plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
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uint32_t num_cpu = ncpu;
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const plat_local_state_t *local_state = states;
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(void)lvl;
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assert(ncpu != 0U);
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do {
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temp = *local_state;
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if ((temp < target)) {
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target = temp;
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}
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--num_cpu;
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local_state++;
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} while (num_cpu != 0U);
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return target;
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}
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/*******************************************************************************
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/*******************************************************************************
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* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
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* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
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* call to get the `power_state` parameter. This allows the platform to encode
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* call to get the `power_state` parameter. This allows the platform to encode
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -100,6 +101,7 @@ int32_t tegra_soc_pwr_domain_on(u_register_t mpidr);
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int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state);
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int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state);
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int32_t tegra_soc_prepare_system_reset(void);
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int32_t tegra_soc_prepare_system_reset(void);
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__dead2 void tegra_soc_prepare_system_off(void);
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__dead2 void tegra_soc_prepare_system_off(void);
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plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
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plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
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/*
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/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -35,6 +36,30 @@
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static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
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static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
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plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
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const plat_local_state_t *states,
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uint32_t ncpu)
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{
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plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
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uint32_t num_cpu = ncpu;
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const plat_local_state_t *local_state = states;
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(void)lvl;
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assert(ncpu != 0U);
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do {
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temp = *local_state;
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if ((temp < target)) {
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target = temp;
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}
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--num_cpu;
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local_state++;
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} while (num_cpu != 0U);
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return target;
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}
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int32_t tegra_soc_validate_power_state(unsigned int power_state,
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int32_t tegra_soc_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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psci_power_state_t *req_state)
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{
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{
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@ -112,6 +137,12 @@ int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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}
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}
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int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
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{
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(void)cpu_state;
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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{
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uint64_t val;
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uint64_t val;
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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}
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}
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int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
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{
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_prepare_system_reset(void)
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int tegra_soc_prepare_system_reset(void)
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{
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{
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/*
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/*
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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}
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}
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__dead2 void tegra_soc_prepare_system_off(void)
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{
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ERROR("Tegra System Off: operation not handled.\n");
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panic();
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}
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/*
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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return ret;
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return ret;
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}
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}
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int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
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{
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(void)cpu_state;
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return PSCI_E_SUCCESS;
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}
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int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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{
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const plat_local_state_t *pwr_domain_state;
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const plat_local_state_t *pwr_domain_state;
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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}
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}
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int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
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int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
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{
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{
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int32_t ret = PSCI_E_SUCCESS;
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int32_t ret = PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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}
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}
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int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
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int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
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{
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{
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uint64_t target_cpu = mpidr & MPIDR_CPU_MASK;
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uint64_t target_cpu = mpidr & MPIDR_CPU_MASK;
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/*
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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return target;
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return target;
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}
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}
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int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
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{
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(void)cpu_state;
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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{
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u_register_t mpidr = read_mpidr();
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u_register_t mpidr = read_mpidr();
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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}
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}
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int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
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{
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return PSCI_E_NOT_SUPPORTED;
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}
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int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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{
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const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
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const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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}
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}
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__dead2 void tegra_soc_prepare_system_off(void)
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{
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ERROR("Tegra System Off: operation not handled.\n");
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panic();
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}
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