ARM plat changes to enable CryptoCell integration
This patch makes the necessary changes to enable ARM platform to successfully integrate CryptoCell during Trusted Board Boot. The changes are as follows: * A new build option `ARM_CRYPTOCELL_INTEG` is introduced to select the CryptoCell crypto driver for Trusted Board boot. * The TrustZone filter settings for Non Secure DRAM is modified to allow CryptoCell to read this memory. This is required to authenticate BL33 which is loaded into the Non Secure DDR. * The CSS platforms are modified to use coherent stacks in BL1 and BL2 when CryptoCell crypto is selected. This is because CryptoCell makes use of DMA to transfer data and the CryptoCell SBROM library allocates buffers on the stack during signature/hash verification. Change-Id: I1e6f6dcd1899784f1edeabfa2a9f279bbfb90e31 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
This commit is contained in:
Soby Mathew
parent
4eb20d99c5
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e60f2af949
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@ -299,6 +299,12 @@ also be defined:
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Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
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FWU content certificate.
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* **#define : PLAT_CRYPTOCELL_BASE**
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This defines the base address of ARM® TrustZone® CryptoCell and must be
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defined if CryptoCell crypto driver is used for Trusted Board Boot. For
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capable ARM platforms, this driver is used if `ARM_CRYPTOCELL_INTEG` is
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set.
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If the AP Firmware Updater Configuration image, BL2U is used, the following
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must also be defined:
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@ -623,6 +623,11 @@ performed.
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with version 1 of the translation tables library instead of version 2. It is
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set to 0 by default, which selects version 2.
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* `ARM_CRYPTOCELL_INTEG` : bool option to enable Trusted Firmware to invoke
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ARM® TrustZone® CryptoCell functionality for Trusted Board Boot on capable
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ARM platforms. If this option is specified, then the path to the CryptoCell
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SBROM library must be specified via `CCSBROM_LIB_PATH` flag.
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For a better understanding of these options, the ARM development platform memory
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map is explained in the [Firmware Design].
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@ -83,6 +83,18 @@
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#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
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ARM_AP_TZC_DRAM1_SIZE - 1)
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/* Define the Access permissions for Secure peripherals to NS_DRAM */
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#if ARM_CRYPTOCELL_INTEG
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/*
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* Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
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* This is required by CryptoCell to authenticate BL33 which is loaded
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* into the Non Secure DDR.
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*/
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#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
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#else
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#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
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#endif
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#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
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#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
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@ -26,6 +26,9 @@
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#define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \
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JUNO_CLUSTER1_CORE_COUNT)
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/* Cryptocell HW Base address */
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#define PLAT_CRYPTOCELL_BASE 0x60050000
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/*
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* Other platform porting definitions are provided by included headers
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*/
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@ -115,3 +115,51 @@ func arm_disable_spe
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ret
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endfunc arm_disable_spe
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#endif
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/*
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* Need to use coherent stack when ARM Cryptocell is used to autheticate images
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* since Cryptocell uses DMA to transfer data and it is not coherent with the
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* AP CPU.
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*/
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#if ARM_CRYPTOCELL_INTEG
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#if defined(IMAGE_BL1) || defined(IMAGE_BL2)
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.globl plat_get_my_stack
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.globl plat_set_my_stack
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.local platform_coherent_stacks
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/* -------------------------------------------------------
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* uintptr_t plat_get_my_stack ()
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*
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* For cold-boot BL images, only the primary CPU needs a
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* stack. This function returns the stack pointer for a
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* stack allocated in coherent memory.
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* -------------------------------------------------------
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*/
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func plat_get_my_stack
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get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE
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ret
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endfunc plat_get_my_stack
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/* -------------------------------------------------------
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* void plat_set_my_stack ()
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*
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* For cold-boot BL images, only the primary CPU needs a
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* stack. This function sets the stack pointer to a stack
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* allocated in coherent memory.
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* -------------------------------------------------------
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*/
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func plat_set_my_stack
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get_up_stack platform_coherent_stacks, PLATFORM_STACK_SIZE
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mov sp, x0
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ret
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endfunc plat_set_my_stack
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/* ----------------------------------------------------
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* Single cpu stack in coherent memory.
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* ----------------------------------------------------
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*/
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declare_stack platform_coherent_stacks, tzfw_coherent_mem, \
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PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE
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#endif /* defined(IMAGE_BL1) || defined(IMAGE_BL2) */
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#endif /* ARM_CRYPTOCELL_INTEG */
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@ -94,6 +94,11 @@ LOAD_IMAGE_V2 := 1
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# Use generic OID definition (tbbr_oid.h)
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USE_TBBR_DEFS := 1
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# Disable ARM Cryptocell by default
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ARM_CRYPTOCELL_INTEG := 0
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$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
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$(eval $(call add_define,ARM_CRYPTOCELL_INTEG))
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PLAT_INCLUDES += -Iinclude/common/tbbr \
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-Iinclude/plat/arm/common
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@ -181,7 +186,11 @@ ifneq (${TRUSTED_BOARD_BOOT},0)
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TF_MBEDTLS_KEY_ALG := ${KEY_ALG}
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# We expect to locate the *.mk files under the directories specified below
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ifeq (${ARM_CRYPTOCELL_INTEG},0)
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CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk
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else
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CRYPTO_LIB_MK := drivers/auth/cryptocell/cryptocell_crypto.mk
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endif
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IMG_PARSER_LIB_MK := drivers/auth/mbedtls/mbedtls_x509.mk
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$(info Including ${CRYPTO_LIB_MK})
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@ -34,6 +34,7 @@ void arm_tzc400_setup(void)
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tzc400_disable_filters();
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#ifndef EL3_PAYLOAD_BASE
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/* Region 0 set to no access by default */
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tzc400_configure_region0(TZC_REGION_S_NONE, 0);
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@ -47,13 +48,13 @@ void arm_tzc400_setup(void)
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* Apply the same configuration to given filters in the TZC. */
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tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 2,
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ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END,
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TZC_REGION_S_NONE,
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ARM_TZC_NS_DRAM_S_ACCESS,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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/* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
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tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 3,
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ARM_DRAM2_BASE, ARM_DRAM2_END,
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TZC_REGION_S_NONE,
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ARM_TZC_NS_DRAM_S_ACCESS,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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#else
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/* Allow secure access only to DRAM for EL3 payloads. */
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@ -41,14 +41,14 @@ void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data)
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tzc_dmc500_configure_region(2,
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ARM_NS_DRAM1_BASE,
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ARM_NS_DRAM1_END,
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TZC_REGION_S_NONE,
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ARM_TZC_NS_DRAM_S_ACCESS,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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/* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
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tzc_dmc500_configure_region(3,
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ARM_DRAM2_BASE,
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ARM_DRAM2_END,
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TZC_REGION_S_NONE,
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ARM_TZC_NS_DRAM_S_ACCESS,
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PLAT_ARM_TZC_NS_DEV_ACCESS);
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#else
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/* Allow secure access only to DRAM for EL3 payloads */
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