From e62ae2e27d35bc7507d3e41086595d6b244596ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 8 Dec 2021 01:33:38 +0100 Subject: [PATCH] refactor(drivers/marvell/comphy-3700): rename Clock Source Low value constants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The constants BUNDLE_PERIOD_SCALE and PLL_READY_DLY refer to two multi-bit registers within the Clock Source Low register. These constants are used as masks for those registers (and values are not defined since we are writing zeros to them). Give them the _MASK suffix. Signed-off-by: Marek Behún Change-Id: Id469d0ab4c755d2d6a0150a1ade33dd9d0293667 --- drivers/marvell/comphy/phy-comphy-3700.c | 5 +++-- drivers/marvell/comphy/phy-comphy-3700.h | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c index 7d84fa53b..1a97753f3 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.c +++ b/drivers/marvell/comphy/phy-comphy-3700.c @@ -678,8 +678,9 @@ static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index, * set Mode Clock Source = PCLK is generated from REFCLK */ usb3_reg_set(reg_base, COMPHY_CLK_SRC_LO, 0x0, - (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE | - BUNDLE_SAMPLE_CTRL | PLL_READY_DLY)); + (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | + BUNDLE_PERIOD_SCALE_MASK | BUNDLE_SAMPLE_CTRL | + PLL_READY_DLY_MASK)); /* * 6. Set G2 Spread Spectrum Clock Amplitude at 4K diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h index 67f2eff82..ed0762482 100644 --- a/drivers/marvell/comphy/phy-comphy-3700.h +++ b/drivers/marvell/comphy/phy-comphy-3700.h @@ -180,9 +180,9 @@ enum { #define CLK_SRC_LO_ADDR(unit) (COMPHY_CLK_SRC_LO * PHY_SHFT(unit)) #define MODE_CLK_SRC BIT(0) #define BUNDLE_PERIOD_SEL BIT(1) -#define BUNDLE_PERIOD_SCALE (BIT(2) | BIT(3)) +#define BUNDLE_PERIOD_SCALE_MASK (BIT(2) | BIT(3)) #define BUNDLE_SAMPLE_CTRL BIT(4) -#define PLL_READY_DLY (BIT(5) | BIT(6) | BIT(7)) +#define PLL_READY_DLY_MASK (BIT(5) | BIT(6) | BIT(7)) #define CFG_SEL_20B BIT(15) #define COMPHY_PWR_MGM_TIM1 0x1D0