Tegra186: re-configure MSS' client settings
This patch reprograms MSS to make ROC deal with ordering of MC traffic after boot and system suspend exit. This is needed as device boots with MSS having all control but POR wants ROC to deal with the ordering. Performance is expected to improve with ROC but since no one has really tested the performance, keep the option configurable for now by introducing a platform level makefile variable. Change-Id: I2e782fea138ccf9d281eb043a6b2c3bb97c839a7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
parent
891685a511
commit
e64ce3abb3
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@ -234,6 +234,251 @@ const static mc_txn_override_cfg_t mc_override_cfgs[] = {
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mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
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};
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static void tegra_memctrl_reconfig_mss_clients(void)
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{
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#if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS
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uint32_t val, wdata_0, wdata_1;
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/*
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* Assert Memory Controller's HOTRESET_FLUSH_ENABLE signal for
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* boot and strongly ordered MSS clients to flush existing memory
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* traffic and stall future requests.
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*/
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
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assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
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wdata_0 = MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
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} while ((val & wdata_0) != wdata_0);
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/* Wait one more time due to SW WAR for known legacy issue */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
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} while ((val & wdata_0) != wdata_0);
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
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assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL);
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wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB;
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
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} while ((val & wdata_1) != wdata_1);
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/* Wait one more time due to SW WAR for known legacy issue */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
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} while ((val & wdata_1) != wdata_1);
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/*
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* Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
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* strongly ordered MSS clients. ROC needs to be single point
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* of control on overriding the memory type. So, remove TSA's
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* memtype override.
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*/
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mc_set_tsa_passthrough(AFIW);
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mc_set_tsa_passthrough(HDAW);
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mc_set_tsa_passthrough(SATAW);
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mc_set_tsa_passthrough(XUSB_HOSTW);
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mc_set_tsa_passthrough(XUSB_DEVW);
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mc_set_tsa_passthrough(SDMMCWAB);
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mc_set_tsa_passthrough(APEDMAW);
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mc_set_tsa_passthrough(SESWR);
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mc_set_tsa_passthrough(ETRW);
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mc_set_tsa_passthrough(AXISW);
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mc_set_tsa_passthrough(EQOSW);
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mc_set_tsa_passthrough(UFSHCW);
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mc_set_tsa_passthrough(BPMPDMAW);
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mc_set_tsa_passthrough(AONDMAW);
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mc_set_tsa_passthrough(SCEDMAW);
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/*
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* Change COH_PATH_OVERRIDE_SO_DEV from NO_OVERRIDE -> FORCE_COHERENT
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* for boot and strongly ordered MSS clients. This steers all sodev
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* transactions to ROC.
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*
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* Change AXID_OVERRIDE/AXID_OVERRIDE_SO_DEV only for some clients
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* whose AXI IDs we know and trust.
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*/
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/* Match AFIW */
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mc_set_forced_coherent_so_dev_cfg(AFIR);
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/*
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* See bug 200131110 comment #35 - there are no normal requests
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* and AWID for SO/DEV requests is hardcoded in RTL for a
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* particular PCIE controller
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*/
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mc_set_forced_coherent_so_dev_cfg(AFIW);
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mc_set_forced_coherent_cfg(HDAR);
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mc_set_forced_coherent_cfg(HDAW);
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mc_set_forced_coherent_cfg(SATAR);
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mc_set_forced_coherent_cfg(SATAW);
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mc_set_forced_coherent_cfg(XUSB_HOSTR);
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mc_set_forced_coherent_cfg(XUSB_HOSTW);
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mc_set_forced_coherent_cfg(XUSB_DEVR);
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mc_set_forced_coherent_cfg(XUSB_DEVW);
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mc_set_forced_coherent_cfg(SDMMCRAB);
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mc_set_forced_coherent_cfg(SDMMCWAB);
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/* Match APEDMAW */
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mc_set_forced_coherent_axid_so_dev_cfg(APEDMAR);
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/*
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* See bug 200131110 comment #35 - AWID for normal requests
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* is 0x80 and AWID for SO/DEV requests is 0x01
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*/
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mc_set_forced_coherent_axid_so_dev_cfg(APEDMAW);
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mc_set_forced_coherent_cfg(SESRD);
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mc_set_forced_coherent_cfg(SESWR);
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mc_set_forced_coherent_cfg(ETRR);
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mc_set_forced_coherent_cfg(ETRW);
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mc_set_forced_coherent_cfg(AXISR);
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mc_set_forced_coherent_cfg(AXISW);
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mc_set_forced_coherent_cfg(EQOSR);
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mc_set_forced_coherent_cfg(EQOSW);
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mc_set_forced_coherent_cfg(UFSHCR);
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mc_set_forced_coherent_cfg(UFSHCW);
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mc_set_forced_coherent_cfg(BPMPDMAR);
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mc_set_forced_coherent_cfg(BPMPDMAW);
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mc_set_forced_coherent_cfg(AONDMAR);
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mc_set_forced_coherent_cfg(AONDMAW);
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mc_set_forced_coherent_cfg(SCEDMAR);
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mc_set_forced_coherent_cfg(SCEDMAW);
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/*
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* At this point, ordering can occur at ROC. So, remove PCFIFO's
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* control over ordering requests.
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*
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* Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
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* boot and strongly ordered MSS clients
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*/
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val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
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mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
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mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
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mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
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tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
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val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
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mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
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mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_DEVW);
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tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val);
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val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
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mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB);
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tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val);
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val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
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mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
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mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, EQOSW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
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tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val);
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val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
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mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW);
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tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val);
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/*
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* At this point, ordering can occur at ROC. SMMU need not
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* reorder any requests.
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*
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* Change SMMU_*_ORDERED_CLIENT from ORDERED -> UNORDERED
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* for boot and strongly ordered MSS clients
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*/
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val = MC_SMMU_CLIENT_CONFIG1_RESET_VAL &
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mc_set_smmu_unordered_boot_so_mss(1, AFIW) &
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mc_set_smmu_unordered_boot_so_mss(1, HDAW) &
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mc_set_smmu_unordered_boot_so_mss(1, SATAW);
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tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG1, val);
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val = MC_SMMU_CLIENT_CONFIG2_RESET_VAL &
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mc_set_smmu_unordered_boot_so_mss(2, XUSB_HOSTW) &
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mc_set_smmu_unordered_boot_so_mss(2, XUSB_DEVW);
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tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG2, val);
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val = MC_SMMU_CLIENT_CONFIG3_RESET_VAL &
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mc_set_smmu_unordered_boot_so_mss(3, SDMMCWAB);
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tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG3, val);
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val = MC_SMMU_CLIENT_CONFIG4_RESET_VAL &
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mc_set_smmu_unordered_boot_so_mss(4, SESWR) &
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mc_set_smmu_unordered_boot_so_mss(4, ETRW) &
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mc_set_smmu_unordered_boot_so_mss(4, AXISW) &
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mc_set_smmu_unordered_boot_so_mss(4, EQOSW) &
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mc_set_smmu_unordered_boot_so_mss(4, UFSHCW) &
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mc_set_smmu_unordered_boot_so_mss(4, BPMPDMAW) &
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mc_set_smmu_unordered_boot_so_mss(4, AONDMAW) &
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mc_set_smmu_unordered_boot_so_mss(4, SCEDMAW);
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tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG4, val);
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val = MC_SMMU_CLIENT_CONFIG5_RESET_VAL &
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mc_set_smmu_unordered_boot_so_mss(5, APEDMAW);
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tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG5, val);
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/*
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* Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS
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* clients to allow memory traffic from all clients to start passing
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* through ROC
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*/
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
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assert(val == wdata_0);
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wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
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} while ((val & wdata_0) != wdata_0);
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/* Wait one more time due to SW WAR for known legacy issue */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
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} while ((val & wdata_0) != wdata_0);
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
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assert(val == wdata_1);
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wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
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} while ((val & wdata_1) != wdata_1);
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/* Wait one more time due to SW WAR for known legacy issue */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
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} while ((val & wdata_1) != wdata_1);
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#endif
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}
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/*
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* Init Memory controller during boot.
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*/
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@ -280,6 +525,14 @@ void tegra_memctrl_setup(void)
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tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
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MC_SMMU_BYPASS_CONFIG_SETTINGS);
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/*
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* Re-configure MSS to allow ROC to deal with ordering of the
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* Memory Controller traffic. This is needed as the Memory Controller
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* boots with MSS having all control, but ROC provides a performance
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* boost as compared to MSS.
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*/
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tegra_memctrl_reconfig_mss_clients();
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/*
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* Set the MC_TXN_OVERRIDE registers for write clients.
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*/
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@ -322,6 +575,14 @@ void tegra_memctrl_setup(void)
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*/
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void tegra_memctrl_restore_settings(void)
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{
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/*
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* Re-configure MSS to allow ROC to deal with ordering of the
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* Memory Controller traffic. This is needed as the Memory Controller
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* resets during System Suspend with MSS having all control, but ROC
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* provides a performance boost as compared to MSS.
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*/
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tegra_memctrl_reconfig_mss_clients();
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/* video memory carveout region */
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if (video_mem_base) {
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
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@ -283,6 +283,10 @@
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#define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188
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#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0
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#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1 << 0)
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#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2 << 4)
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#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1 << 12)
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/*******************************************************************************
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* Non-SO_DEV transactions override values for CGID_TAG bitfield for the
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* MC_TXN_OVERRIDE_CONFIG_{module} registers
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@ -327,12 +331,12 @@ typedef struct mc_streamid_security_cfg {
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int override_client_ns_flag;
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} mc_streamid_security_cfg_t;
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#define OVERRIDE_DISABLE 1
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#define OVERRIDE_ENABLE 0
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#define CLIENT_FLAG_SECURE 0
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#define CLIENT_FLAG_NON_SECURE 1
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#define CLIENT_INPUTS_OVERRIDE 1
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#define CLIENT_INPUTS_NO_OVERRIDE 0
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#define OVERRIDE_DISABLE 1
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#define OVERRIDE_ENABLE 0
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#define CLIENT_FLAG_SECURE 0
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#define CLIENT_FLAG_NON_SECURE 1
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#define CLIENT_INPUTS_OVERRIDE 1
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#define CLIENT_INPUTS_NO_OVERRIDE 0
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#define mc_make_sec_cfg(off, ns, ovrrd, access) \
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{ \
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@ -346,27 +350,200 @@ typedef struct mc_streamid_security_cfg {
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/*******************************************************************************
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* TZDRAM carveout configuration registers
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******************************************************************************/
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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#define MC_SECURITY_CFG3_0 0x9BC
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#define MC_SECURITY_CFG0_0 0x70
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#define MC_SECURITY_CFG1_0 0x74
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#define MC_SECURITY_CFG3_0 0x9BC
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/*******************************************************************************
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* Video Memory carveout configuration registers
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******************************************************************************/
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#define MC_VIDEO_PROTECT_BASE_HI 0x978
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#define MC_VIDEO_PROTECT_BASE_LO 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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#define MC_VIDEO_PROTECT_BASE_HI 0x978
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#define MC_VIDEO_PROTECT_BASE_LO 0x648
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#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
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/*******************************************************************************
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* TZRAM carveout configuration registers
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******************************************************************************/
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#define MC_TZRAM_BASE 0x1850
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#define MC_TZRAM_END 0x1854
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#define MC_TZRAM_HI_ADDR_BITS 0x1588
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#define TZRAM_ADDR_HI_BITS_MASK 0x3
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#define TZRAM_END_HI_BITS_SHIFT 8
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#define MC_TZRAM_REG_CTRL 0x185c
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#define DISABLE_TZRAM_ACCESS 1
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#define MC_TZRAM_BASE 0x1850
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#define MC_TZRAM_END 0x1854
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#define MC_TZRAM_HI_ADDR_BITS 0x1588
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#define TZRAM_ADDR_HI_BITS_MASK 0x3
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#define TZRAM_END_HI_BITS_SHIFT 8
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#define MC_TZRAM_REG_CTRL 0x185c
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#define DISABLE_TZRAM_ACCESS 1
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/*******************************************************************************
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* Memory Controller Reset Control registers
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******************************************************************************/
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#define MC_CLIENT_HOTRESET_CTRL0 0x200
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#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0
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#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1 << 0)
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#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1 << 6)
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#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1 << 7)
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#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1 << 8)
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#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1 << 9)
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#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1 << 11)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1 << 15)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1 << 17)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1 << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1 << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1 << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1 << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1 << 29)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1 << 30)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1 << 31)
|
||||
#define MC_CLIENT_HOTRESET_STATUS0 0x204
|
||||
#define MC_CLIENT_HOTRESET_CTRL1 0x970
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1 << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1 << 2)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1 << 5)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1 << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1 << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1 << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1 << 12)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1 << 13)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1 << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1 << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1 << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1 << 21)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1 << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1 << 23)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1 << 24)
|
||||
#define MC_CLIENT_HOTRESET_STATUS1 0x974
|
||||
|
||||
/*******************************************************************************
|
||||
* TSA configuration registers
|
||||
******************************************************************************/
|
||||
#define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010
|
||||
#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038
|
||||
#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010
|
||||
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008
|
||||
#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008
|
||||
#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100
|
||||
#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018
|
||||
#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018
|
||||
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028
|
||||
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018
|
||||
#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008
|
||||
#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018
|
||||
#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028
|
||||
#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038
|
||||
#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008
|
||||
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100
|
||||
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018
|
||||
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100
|
||||
|
||||
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11)
|
||||
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11)
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller's PCFIFO client configuration registers
|
||||
******************************************************************************/
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0 << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1 << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0 << 21)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1 << 21)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0 << 29)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1 << 29)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0 << 11)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1 << 11)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0 << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1 << 13)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3 0xddc
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0 << 7)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1 << 7)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0 << 1)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1 << 1)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0 << 5)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1 << 5)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0 << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1 << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0 << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1 << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0 << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1 << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0 << 22)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1 << 22)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0 << 26)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1 << 26)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0 << 30)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1 << 30)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0 << 0)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1 << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller's SMMU client configuration registers
|
||||
******************************************************************************/
|
||||
#define MC_SMMU_CLIENT_CONFIG1 0x44
|
||||
#define MC_SMMU_CLIENT_CONFIG1_RESET_VAL 0x20000
|
||||
#define MC_SMMU_CLIENT_CONFIG1_AFIW_UNORDERED (0 << 17)
|
||||
#define MC_SMMU_CLIENT_CONFIG1_AFIW_MASK (1 << 17)
|
||||
#define MC_SMMU_CLIENT_CONFIG1_HDAW_UNORDERED (0 << 21)
|
||||
#define MC_SMMU_CLIENT_CONFIG1_HDAW_MASK (1 << 21)
|
||||
#define MC_SMMU_CLIENT_CONFIG1_SATAW_UNORDERED (0 << 29)
|
||||
#define MC_SMMU_CLIENT_CONFIG1_SATAW_MASK (1 << 29)
|
||||
|
||||
#define MC_SMMU_CLIENT_CONFIG2 0x48
|
||||
#define MC_SMMU_CLIENT_CONFIG2_RESET_VAL 0x20000
|
||||
#define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_UNORDERED (0 << 11)
|
||||
#define MC_SMMU_CLIENT_CONFIG2_XUSB_HOSTW_MASK (1 << 11)
|
||||
#define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_UNORDERED (0 << 13)
|
||||
#define MC_SMMU_CLIENT_CONFIG2_XUSB_DEVW_MASK (1 << 13)
|
||||
|
||||
#define MC_SMMU_CLIENT_CONFIG3 0x4c
|
||||
#define MC_SMMU_CLIENT_CONFIG3_RESET_VAL 0
|
||||
#define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_UNORDERED (0 << 7)
|
||||
#define MC_SMMU_CLIENT_CONFIG3_SDMMCWAB_MASK (1 << 7)
|
||||
|
||||
#define MC_SMMU_CLIENT_CONFIG4 0xb9c
|
||||
#define MC_SMMU_CLIENT_CONFIG4_RESET_VAL 0
|
||||
#define MC_SMMU_CLIENT_CONFIG4_SESWR_UNORDERED (0 << 1)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_SESWR_MASK (1 << 1)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_ETRW_UNORDERED (0 << 5)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_ETRW_MASK (1 << 5)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_AXISW_UNORDERED (0 << 13)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_AXISW_MASK (1 << 13)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_EQOSW_UNORDERED (0 << 15)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_EQOSW_MASK (1 << 15)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_UFSHCW_UNORDERED (0 << 17)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_UFSHCW_MASK (1 << 17)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_UNORDERED (0 << 22)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_BPMPDMAW_MASK (1 << 22)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_AONDMAW_UNORDERED (0 << 26)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_AONDMAW_MASK (1 << 26)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_UNORDERED (0 << 30)
|
||||
#define MC_SMMU_CLIENT_CONFIG4_SCEDMAW_MASK (1 << 30)
|
||||
|
||||
#define MC_SMMU_CLIENT_CONFIG5 0xbac
|
||||
#define MC_SMMU_CLIENT_CONFIG5_RESET_VAL 0
|
||||
#define MC_SMMU_CLIENT_CONFIG5_APEDMAW_UNORDERED (0 << 0)
|
||||
#define MC_SMMU_CLIENT_CONFIG5_APEDMAW_MASK (1 << 0)
|
||||
|
||||
static inline uint32_t tegra_mc_read_32(uint32_t off)
|
||||
{
|
||||
|
|
@ -388,4 +565,41 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
|
|||
mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val);
|
||||
}
|
||||
|
||||
#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
|
||||
(~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
|
||||
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
|
||||
|
||||
#define mc_set_smmu_unordered_boot_so_mss(id, client) \
|
||||
(~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
|
||||
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
|
||||
|
||||
#define mc_set_tsa_passthrough(client) \
|
||||
{ \
|
||||
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
|
||||
(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
|
||||
~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
|
||||
TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
|
||||
}
|
||||
|
||||
#define mc_set_forced_coherent_cfg(client) \
|
||||
{ \
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
|
||||
MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV); \
|
||||
}
|
||||
|
||||
#define mc_set_forced_coherent_so_dev_cfg(client) \
|
||||
{ \
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
|
||||
MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \
|
||||
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \
|
||||
}
|
||||
|
||||
#define mc_set_forced_coherent_axid_so_dev_cfg(client) \
|
||||
{ \
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
|
||||
MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV | \
|
||||
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID | \
|
||||
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \
|
||||
}
|
||||
|
||||
#endif /* __MEMCTRLV2_H__ */
|
||||
|
|
|
|||
|
|
@ -83,6 +83,11 @@
|
|||
#define HARDWARE_REVISION_A01 1
|
||||
#define MISCREG_PFCFG 0x200C
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra TSA Controller constants
|
||||
******************************************************************************/
|
||||
#define TEGRA_TSA_BASE 0x02400000
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra Memory Controller constants
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -65,6 +65,8 @@ const unsigned char tegra_power_domain_tree_desc[] = {
|
|||
static const mmap_region_t tegra_mmap[] = {
|
||||
MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
|
||||
MT_DEVICE | MT_RW | MT_SECURE),
|
||||
MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
|
||||
|
|
|
|||
|
|
@ -32,6 +32,9 @@
|
|||
ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1
|
||||
$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS))
|
||||
|
||||
ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1
|
||||
$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
|
||||
|
||||
# platform settings
|
||||
TZDRAM_BASE := 0x30000000
|
||||
$(eval $(call add_define,TZDRAM_BASE))
|
||||
|
|
@ -42,10 +45,10 @@ $(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
|
|||
PLATFORM_MAX_CPUS_PER_CLUSTER := 4
|
||||
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
|
||||
|
||||
MAX_XLAT_TABLES := 15
|
||||
MAX_XLAT_TABLES := 16
|
||||
$(eval $(call add_define,MAX_XLAT_TABLES))
|
||||
|
||||
MAX_MMAP_REGIONS := 15
|
||||
MAX_MMAP_REGIONS := 16
|
||||
$(eval $(call add_define,MAX_MMAP_REGIONS))
|
||||
|
||||
# platform files
|
||||
|
|
|
|||
Loading…
Reference in New Issue