Add workaround for errata 855423 of Cortex-A73
Broadcast maintainance operations might not be correctly synchronized between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this. Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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@ -132,6 +132,11 @@ For Cortex-A72, the following errata build flags are defined :
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- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
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CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
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For Cortex-A73, the following errata build flags are defined :
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- ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
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CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
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DSU Errata Workarounds
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----------------------
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@ -31,4 +31,6 @@
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#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3)
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#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2
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#endif /* CORTEX_A73_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -35,7 +35,47 @@ func cortex_a73_disable_smp
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ret
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endfunc cortex_a73_disable_smp
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A73 Errata #855423.
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* This applies only to revision <= r0p1 of Cortex A73.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------
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*/
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func errata_a73_855423_wa
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/*
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* Compare x0 against revision r0p1
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*/
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mov x17, x30
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bl check_errata_855423
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cbz x0, 1f
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mrs x1, CORTEX_A73_IMP_DEF_REG2
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orr x1, x1, #(1 << 7)
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msr CORTEX_A73_IMP_DEF_REG2, x1
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isb
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1:
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ret x17
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endfunc errata_a73_855423_wa
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func check_errata_855423
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mov x1, #0x01
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b cpu_rev_var_ls
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endfunc check_errata_855423
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A73.
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* -------------------------------------------------
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*/
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func cortex_a73_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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#if ERRATA_A73_855423
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bl errata_a73_855423_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
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cpu_check_csv2 x0, 1f
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adr x0, wa_cve_2017_5715_bpiall_vbar
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@ -60,7 +100,7 @@ func cortex_a73_reset_func
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orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
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msr CORTEX_A73_CPUECTLR_EL1, x0
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isb
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ret
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ret x19
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endfunc cortex_a73_reset_func
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func cortex_a73_core_pwr_dwn
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@ -160,6 +200,7 @@ func cortex_a73_errata_report
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A73_855423, cortex_a73, 855423
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report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
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report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639
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@ -119,6 +119,10 @@ ERRATA_A57_859972 ?=0
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# only to revision <= r0p3 of the Cortex A72 cpu.
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ERRATA_A72_859971 ?=0
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# Flag to apply erratum 855423 workaround during reset. This erratum applies
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# only to revision <= r0p1 of the Cortex A73 cpu.
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ERRATA_A73_855423 ?=0
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# Flag to apply T32 CLREX workaround during reset. This erratum applies
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# only to r0p0 and r1p0 of the Neoverse N1 cpu.
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ERRATA_N1_1043202 ?=1
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@ -188,6 +192,10 @@ $(eval $(call add_define,ERRATA_A57_859972))
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$(eval $(call assert_boolean,ERRATA_A72_859971))
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$(eval $(call add_define,ERRATA_A72_859971))
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# Process ERRATA_A73_855423 flag
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$(eval $(call assert_boolean,ERRATA_A73_855423))
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$(eval $(call add_define,ERRATA_A73_855423))
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# Process ERRATA_N1_1043202 flag
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$(eval $(call assert_boolean,ERRATA_N1_1043202))
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$(eval $(call add_define,ERRATA_N1_1043202))
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