imx: power optimization for i.mx8qx
Current implementation of i.MX8QX power management related features does NOT optimize power number, all system resources like CCI, DDR, and A cluster etc. are kept in STBY mode (powered ON) when system suspend or CPU hotplug. To lower the power number, OFF mode should be adopted for those system resources whenever they can be OFF, A cluster will be OFF if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF if system suspend, IRQ steer can be OFF if the wakeup source is belonged to system controller partition, so wakeup source runtime check is used to determine if IRQ steer can be OFF before system suspend. If resources are powered off for suspend, they should be restored properly after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
This commit is contained in:
Anson Huang
parent
3a2b51993d
commit
e6cf7a468e
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@ -44,10 +44,7 @@ static entry_point_info_t bl33_image_ep_info;
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(SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT))
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static const mmap_region_t imx_mmap[] = {
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MAP_REGION_FLAT(IMX_BOOT_UART_BASE, IMX_BOOT_UART_SIZE, MT_DEVICE | MT_RW),
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MAP_REGION_FLAT(SC_IPC_BASE, SC_IPC_SIZE, MT_DEVICE | MT_RW),
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MAP_REGION_FLAT(PLAT_GICD_BASE, PLAT_GICD_SIZE, MT_DEVICE | MT_RW),
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MAP_REGION_FLAT(PLAT_GICR_BASE, PLAT_GICR_SIZE, MT_DEVICE | MT_RW),
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MAP_REGION_FLAT(IMX_REG_BASE, IMX_REG_SIZE, MT_DEVICE | MT_RW),
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{0}
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};
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@ -281,6 +278,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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/* Turn on MU1 for non-secure OS/Hypervisor */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON);
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/* Turn on GPT_0's power & clock for non-secure OS/Hypervisor */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON);
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sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0);
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mmio_write_32(IMX_GPT0_LPCG_BASE, mmio_read_32(IMX_GPT0_LPCG_BASE) | (1 << 25));
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/*
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* create new partition for non-secure OS/Hypervisor
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* uses global structs defined in sec_rsrc.h
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@ -16,10 +16,52 @@
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#include <plat_imx8.h>
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#include <sci/sci.h>
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#include "../../common/sci/imx8_mu.h"
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const static int ap_core_index[PLATFORM_CORE_COUNT] = {
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SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3
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};
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/* save gic dist/redist context when GIC is power down */
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static struct plat_gic_ctx imx_gicv3_ctx;
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static unsigned int gpt_lpcg, gpt_reg[2];
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static void imx_enable_irqstr_wakeup(void)
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{
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uint32_t irq_mask;
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gicv3_dist_ctx_t *dist_ctx = &imx_gicv3_ctx.dist_ctx;
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/* put IRQSTR into ON mode */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_ON);
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/* enable the irqsteer to handle wakeup irq */
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mmio_write_32(IMX_WUP_IRQSTR_BASE, 0x1);
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for (int i = 0; i < 15; i++) {
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irq_mask = dist_ctx->gicd_isenabler[i];
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mmio_write_32(IMX_WUP_IRQSTR_BASE + 0x3c - 0x4 * i, irq_mask);
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}
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/* set IRQSTR low power mode */
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if (imx_is_wakeup_src_irqsteer())
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_STBY);
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else
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_OFF);
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}
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static void imx_disable_irqstr_wakeup(void)
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{
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/* Put IRQSTEER back to ON mode */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_ON);
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/* disable the irqsteer */
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mmio_write_32(IMX_WUP_IRQSTR_BASE, 0x0);
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for (int i = 0; i < 16; i++)
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mmio_write_32(IMX_WUP_IRQSTR_BASE + 0x4 + 0x4 * i, 0x0);
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/* Put IRQSTEER into OFF mode */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_IRQSTR_SCU2, SC_PM_PW_MODE_OFF);
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}
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int imx_pwr_domain_on(u_register_t mpidr)
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{
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int ret = PSCI_E_SUCCESS;
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@ -71,11 +113,52 @@ void imx_domain_suspend(const psci_power_state_t *target_state)
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u_register_t mpidr = read_mpidr_el1();
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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plat_gic_cpuif_disable();
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if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL0])) {
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plat_gic_cpuif_disable();
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sc_pm_set_cpu_resume(ipc_handle, ap_core_index[cpu_id], true, BL31_BASE);
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sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id],
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SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC);
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} else {
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dsb();
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write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
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isb();
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}
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sc_pm_set_cpu_resume_addr(ipc_handle, ap_core_index[cpu_id], BL31_BASE);
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sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id],
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SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC);
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if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1]))
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_OFF);
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if (is_local_state_retn(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL])) {
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plat_gic_cpuif_disable();
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/* save gic context */
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plat_gic_save(cpu_id, &imx_gicv3_ctx);
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/* enable the irqsteer for wakeup */
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imx_enable_irqstr_wakeup();
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/* Save GPT clock and registers, then turn off its power */
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gpt_lpcg = mmio_read_32(IMX_GPT0_LPCG_BASE);
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gpt_reg[0] = mmio_read_32(IMX_GPT0_BASE);
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gpt_reg[1] = mmio_read_32(IMX_GPT0_BASE + 0x4);
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_OFF);
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_OFF);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_DDR,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_MU,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_OFF);
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/* Put GIC in OFF mode. */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_GIC, SC_PM_PW_MODE_OFF);
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sc_pm_set_cpu_resume(ipc_handle, ap_core_index[cpu_id], true, BL31_BASE);
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if (imx_is_wakeup_src_irqsteer())
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sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id],
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SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_IRQSTEER);
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else
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sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id],
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SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_SCU);
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}
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}
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void imx_domain_suspend_finish(const psci_power_state_t *target_state)
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@ -83,10 +166,51 @@ void imx_domain_suspend_finish(const psci_power_state_t *target_state)
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u_register_t mpidr = read_mpidr_el1();
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id],
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SC_PM_PW_MODE_ON);
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if (is_local_state_retn(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL])) {
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MU_Resume(SC_IPC_BASE);
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plat_gic_cpuif_enable();
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sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id], SC_PM_PW_MODE_ON);
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sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id],
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SC_PM_PW_MODE_ON, SC_PM_WAKE_SRC_GIC);
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/* Put GIC back to high power mode. */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_GIC, SC_PM_PW_MODE_ON);
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/* restore gic context */
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plat_gic_restore(cpu_id, &imx_gicv3_ctx);
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/* Turn on GPT power and restore its clock and registers */
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sc_pm_set_resource_power_mode(ipc_handle, SC_R_GPT_0, SC_PM_PW_MODE_ON);
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sc_pm_clock_enable(ipc_handle, SC_R_GPT_0, SC_PM_CLK_PER, true, 0);
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mmio_write_32(IMX_GPT0_BASE, gpt_reg[0]);
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mmio_write_32(IMX_GPT0_BASE + 0x4, gpt_reg[1]);
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mmio_write_32(IMX_GPT0_LPCG_BASE, gpt_lpcg);
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_DDR,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_MU,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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/* disable the irqsteer wakeup */
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imx_disable_irqstr_wakeup();
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plat_gic_cpuif_enable();
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}
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if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL1]))
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_ON);
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if (is_local_state_off(target_state->pwr_domain_state[MPIDR_AFFLVL0])) {
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sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id],
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SC_PM_PW_MODE_ON, SC_PM_WAKE_SRC_GIC);
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plat_gic_cpuif_enable();
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} else {
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write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT));
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isb();
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}
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}
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static const plat_psci_ops_t imx_plat_psci_ops = {
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@ -108,17 +232,15 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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imx_mailbox_init(sec_entrypoint);
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*psci_ops = &imx_plat_psci_ops;
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/* Request low power mode for A35 cluster, only need to do once */
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_OFF);
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/* make sure system sources power ON in low power mode by default */
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_ON);
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/* Request RUN and LP modes for DDR, system interconnect etc. */
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35,
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SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35,
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SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35,
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SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON,
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SC_PM_PW_MODE_STBY);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_DDR,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_MU,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, SC_PM_SYS_IF_INTERCONNECT,
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SC_PM_PW_MODE_ON, SC_PM_PW_MODE_ON);
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return 0;
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}
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@ -37,18 +37,19 @@
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#define MAX_MMAP_REGIONS 8
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#define PLAT_GICD_BASE 0x51a00000
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#define PLAT_GICD_SIZE 0x10000
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#define PLAT_GICR_BASE 0x51b00000
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#define PLAT_GICR_SIZE 0xc0000
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#define IMX_BOOT_UART_BASE 0x5a060000
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#define IMX_BOOT_UART_SIZE 0x1000
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#define IMX_BOOT_UART_BAUDRATE 115200
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#define IMX_BOOT_UART_CLK_IN_HZ 24000000
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#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
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#define PLAT__CRASH_UART_CLK_IN_HZ 24000000
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#define IMX_CONSOLE_BAUDRATE 115200
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#define SC_IPC_BASE 0x5d1b0000
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#define SC_IPC_SIZE 0x10000
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#define IMX_GPT0_LPCG_BASE 0x5d540000
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#define IMX_GPT0_BASE 0x5d140000
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#define IMX_WUP_IRQSTR_BASE 0x51090000
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#define IMX_REG_BASE 0x50000000
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#define IMX_REG_SIZE 0x10000000
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#define COUNTER_FREQUENCY 8000000
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@ -14,10 +14,12 @@ sc_rsrc_t secure_rsrcs[] = {
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SC_R_A35_3,
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SC_R_GIC,
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SC_R_SYSTEM,
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SC_R_IRQSTR_SCU2
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SC_R_IRQSTR_SCU2,
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SC_R_GPT_0
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};
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/* resources that have register access for non-secure domain */
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sc_rsrc_t ns_access_allowed[] = {
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SC_R_GIC,
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SC_R_GPT_0
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};
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